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  • eb8420e7f9 tx/rx buff接口归一化 RuigeLee 2023-10-30 17:32:55 +08:00
  • beedc98977 解耦rx/txlength，txcrc，后面应该整合tilelink模块，统一dma与mac RuigeLee 2023-10-27 18:27:58 +08:00
  • ada2f25ff3 bug清理完成 RuigeLee 2023-10-26 15:46:21 +08:00
  • 530e6d9792 编译完成，bug:1 tx 最后一个字节读取了两次，2 先tx无法rx RuigeLee 2023-10-26 14:59:31 +08:00
  • 694d3890b0 crc cleanup RuigeLee 2023-10-26 11:41:29 +08:00
  • b1629ad0a9 remvoe pad and minFL RuigeLee 2023-10-26 11:32:44 +08:00
  • a59a0d9687 clean maxFL RuigeLee 2023-10-25 18:01:04 +08:00
  • 09ea816005 maccontrol remove RuigeLee 2023-10-25 17:53:18 +08:00
  • 7f8536ec82 maccontrol remove RuigeLee 2023-10-25 17:52:43 +08:00
  • 1e6f2df9ae clean up RuigeLee 2023-10-25 16:04:53 +08:00
  • 6e25f934b2 remove tx toobig RuigeLee 2023-10-25 15:34:43 +08:00
  • 811c540b6b remove tx retry RuigeLee 2023-10-25 15:21:43 +08:00
  • 8fad6fc9cb remove rxabort again RuigeLee 2023-10-25 14:33:48 +08:00
  • 3e4964852e 人机交互界面完成 RuigeLee 2023-10-24 17:42:25 +08:00
  • e99ff4789f tx 首尾修正 RuigeLee 2023-10-24 16:27:30 +08:00
  • 701ba16491 cleanup RuigeLee 2023-10-24 15:34:30 +08:00
  • 86fb086bd2 tx 32转8 基本测试通过 RuigeLee 2023-10-24 14:00:51 +08:00
  • 54991d8cb5 Tx尝试统一接口，失败 RuigeLee 2023-10-23 23:36:01 +08:00
  • faa46be8ef Rx的req resp跨时钟架构 RuigeLee 2023-10-23 22:58:36 +08:00
  • bf66bae475 rx 通道基本完成32转8，存在跨时钟域风险 RuigeLee 2023-10-21 21:08:40 +08:00
  • 69ccc32603 在32数据通道下传输正确 RuigeLee 2023-10-20 20:56:44 +08:00
  • f17d405369 Rx DMA 传输正确 RuigeLee 2023-10-20 15:49:24 +08:00
  • 0215add0d4 rx DMA编译完成 RuigeLee 2023-10-20 14:42:15 +08:00
  • c5f9b4d74f 未完成，尝试建立DMA RuigeLee 2023-10-19 18:31:26 +08:00
  • 70922ecb44 拓扑修改，编译通过 RuigeLee 2023-10-19 15:24:26 +08:00
  • d77c69aa5a 接收数据流解耦初步测试成功 RuigeLee 2023-10-18 17:11:56 +08:00
  • 629d9486d1 完成编译，准备接入CPU查看信号逻辑 RuigeLee 2023-10-17 16:38:18 +08:00
  • 7c71c005f8 基本清理完成 RuigeLee 2023-10-14 12:36:37 +08:00
  • 0c60fbfb15 未完成清理tx，txready初始化为true RuigeLee 2023-10-13 18:18:02 +08:00
  • ceef60b95c 断言不会发生tx Underrun RuigeLee 2023-10-13 15:21:53 +08:00
  • bb35dffb84 未完成tx拆解 RuigeLee 2023-10-12 18:37:12 +08:00
  • af4e95fa47 增加rx功能buff，底座 RuigeLee 2023-10-12 17:04:10 +08:00
  • 38550d723b rx数据通道已经拆解 RuigeLee 2023-10-12 15:42:49 +08:00
  • 774c00a97c 未完成，重构rx tilelink，使能仅依赖于pingpong是否准备好 RuigeLee 2023-10-11 18:48:05 +08:00
  • 82a6805e05 异步fifo RuigeLee 2023-10-10 16:48:32 +08:00
  • 201ab2579b 化简代码 RuigeLee 2023-10-08 18:27:49 +08:00
  • 31d2d86f01 bug:阶跃错误 RuigeLee 2023-10-08 15:54:40 +08:00
  • aec4160431 代码清理 RuigeLee 2023-10-08 15:37:54 +08:00
  • a331599ad4 bug: 信号同步时钟域错误 RuigeLee 2023-10-08 15:30:08 +08:00
  • 92a6f6b5c3 move out rx RuigeLee 2023-10-08 15:13:35 +08:00
  • 115f216139 moveout tx RuigeLee 2023-10-08 11:34:36 +08:00
  • 3b6b3bc14b 增加跨时钟域，准备切换分支 RuigeLee 2023-10-08 10:12:49 +08:00
  • 2435f7fa01 rx初步优化 编译通过 RuigeLee 2023-10-07 16:44:13 +08:00
  • fd0f1347cf 半成品，剥离tilelinkTx，在mtx不会远大于clock；tx_FIFO不会极限小的情况下，无跨时钟保护是允许的 RuigeLee 2023-09-28 18:45:14 +08:00
  • f3a35964f8 opt: tx/rx传输必须32比特对齐，不再支持非对齐操作 RuigeLee 2023-09-27 16:31:56 +08:00
  • 61f15c9ebe bug:rx 大小端总线传输非对齐模式下mask错误 RuigeLee 2023-09-27 16:14:04 +08:00
  • e6f34762e8 状态机化简 RuigeLee 2023-09-26 21:41:19 +08:00
  • 25a5c81668 bug: 异步复位信号缺失 RuigeLee 2023-09-26 21:40:47 +08:00
  • 51c39369c8 要求所有tx/rx时钟域异步复位 RuigeLee 2023-09-25 14:18:27 +08:00
  • 5ff118f527 rx: big-endian to little-endian RuigeLee 2023-09-21 16:55:22 +08:00
  • e42c6a3b11 dma cache to sys-port RuigeLee 2023-09-20 11:17:30 +08:00
  • 8a9aa0436c a sign for tx/rx clock merge RuigeLee 2023-09-19 18:03:30 +08:00
  • 4702991e69 tx: big-endian to little-endian RuigeLee 2023-09-19 17:54:36 +08:00
  • 40b558d3a2 sync RuigeLee 2023-09-15 15:36:44 +08:00
  • b098ca963e test pass RuigeLee 2023-09-14 19:16:17 +08:00
  • 6fd836fc9c new version RuigeLee 2023-09-12 17:51:32 +08:00
  • 527f6bd761 fix sync misunderstanding RuigeLee 2023-09-11 17:39:19 +08:00
  • 05a905ac39 merge mirror read/write RuigeLee 2023-09-08 18:47:13 +08:00
  • bf835014bc 16bit fsmc data; 16*2 reg, 100us RuigeLee 2023-09-08 16:37:31 +08:00
  • 145db92202 test pass RuigeLee 2023-08-31 17:39:12 +08:00
  • d226487a5e BUG FIX RuigeLee 2023-08-31 15:10:18 +08:00
  • 860e24ca99 check mst RuigeLee 2023-08-30 17:32:19 +08:00
  • c0645cfe16 update sram; bug fixed; lvds failed RuigeLee 2023-08-23 19:32:41 +08:00
  • cead446356 io merge Ruige Lee (WSL) 2023-08-22 17:50:31 +08:00
  • 44e8999ab0 switch from 4k to 2k Ruige Lee (WSL) 2023-08-22 15:32:01 +08:00
  • 704996bdfb Merge branch 'main' of github.com:whutddk/RISCV-MAC-SWICH into main Ruige Lee (WSL) 2023-08-22 14:17:55 +08:00
  • a3ce58fb94 add fpga top RuigeLee 2023-08-21 21:14:43 +08:00
  • 37ac7817d7 fix sram Ruige Lee (WSL) 2023-08-21 14:52:21 +08:00
  • 5f15e94ae3 bug override RuigeLee 2023-08-21 11:51:59 +08:00
  • 31a822091b Revert "devide gowin file" RuigeLee 2023-08-21 11:51:25 +08:00
  • d162b8f75c devide gowin file RuigeLee 2023-08-21 11:46:50 +08:00
  • 20ddabbfb3 add submodule RuigeLee 2023-08-21 11:20:16 +08:00
  • 589fc528a0 compile pass RuigeLee 2023-08-20 15:50:11 +08:00
  • f3a44f0b31 slv Ruige Lee 2023-08-18 12:10:47 +00:00
  • 6fa2ef5f6e porta RuigeLee 2023-08-16 22:25:30 +08:00
  • bbd0f0b887 sync Ruige Lee 2023-08-16 06:12:49 +00:00
  • 6c2f0b02f8 FSMC Ruige Lee 2023-08-15 08:42:56 +00:00
  • 939fa22be5 wrapper of mst and slv Ruige Lee 2023-08-15 02:59:10 +00:00
  • 3211e21e11 wrapper RuigeLee 2023-08-14 22:46:50 +08:00
  • 50403930a9 check chain RuigeLee 2023-08-09 16:34:29 +08:00
  • 1c7a226a70 add function demo RuigeLee 2023-08-09 14:43:24 +08:00
  • 68e0a6a055 test pass RuigeLee 2023-08-07 11:40:14 +08:00
  • a041c7732a over sample in spi RuigeLee 2023-08-07 10:15:56 +08:00
  • d09aff40f2 timing close RuigeLee 2023-08-02 15:17:16 +08:00
  • 5d43600680 fpga sync RuigeLee 2023-08-01 15:50:53 +08:00
  • 35e6fcdb52 mst test pass RuigeLee 2023-08-01 14:44:05 +08:00
  • 24800cce9d spi compile pass RuigeLee 2023-07-31 22:56:09 +08:00
  • 0f79860656 revert mdio direction RuigeLee 2023-07-31 09:19:57 +08:00
  • 3aa4ca17d4 all test pass RuigeLee 2023-07-28 20:42:35 +08:00
  • 2048a4d286 first test RuigeLee 2023-07-28 15:38:46 +08:00
  • 85fe9175e6 backplaneslv compile pass Ruige 2023-07-25 21:05:43 +08:00
  • b1fd2db2e0 backboard RuigeLee 2023-07-24 19:31:32 +08:00
  • 440cefb02a we use async reset for different clock now RuigeLee 2023-07-24 19:31:20 +08:00
  • 21f8547273 ethreg Test pass RuigeLee 2023-07-21 16:38:02 +08:00
  • 0b48e2cd2b compile pass RuigeLee 2023-07-20 14:58:59 +08:00
  • fa748b7de9 Revert "create register node" RuigeLee 2023-07-20 10:35:56 +08:00
  • e558356a22 create register node RuigeLee 2023-07-20 10:01:59 +08:00
  • 6cb9d0982e tb remove RuigeLee 2023-07-19 11:30:26 +08:00
  • e3e1f6b6cb a new top for fpga; port mac-master to mem RuigeLee 2023-07-17 21:41:34 +08:00
  • de5eb461f6 sim env RuigeLee 2023-07-17 09:26:20 +08:00