compile pass
This commit is contained in:
RuigeLee
@@ -5,7 +5,7 @@ import chisel3.util._
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class FSMC_Port_Bundle extends Bundle{
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val addr = Input(UInt(12.W))
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val addr = Input(UInt(13.W))
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val dataIn = Input(UInt(8.W))
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val dataOut = Output(UInt(8.W))
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val dataOEn = Output(Bool())
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@@ -38,8 +38,8 @@ class BackBoardMstBase extends RawModule{
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val mirrorDown = Module(new MirrorSRAM)
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val mirrorUp = Module(new MirrorSRAM)
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val status = Reg(UInt(8.W))
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val slvNum = Reg(UInt(5.W))
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val status = Wire(UInt(8.W))
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val slvNum = Wire(UInt(5.W))
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mirrorDown.io.clock := io.ides_pclk.asBool
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@@ -54,6 +54,9 @@ class BackBoardMstBase extends RawModule{
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trait BackBoardMstFSMC{ this: BackBoardMstBase =>
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withClockAndReset( io.ides_pclk.asClock, io.reset ){
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val statusReg = RegInit(0.U(8.W)); status := statusReg
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val slvNumReg = RegInit(0.U(5.W)); slvNum := slvNumReg
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val fsmcAddrSync = ShiftRegister( io.FSMC.addr, 2, 0.U, true.B )
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val fsmcdataInSync = ShiftRegister( io.FSMC.dataIn, 2, 0.U, true.B )
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val fsmcCEnSync = ShiftRegister( io.FSMC.cen, 2, true.B, true.B )
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@@ -82,11 +85,11 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
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))
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when( (~fsmcCEnSync & fsmcAddrSync.extract(12) & (~fsmcWEnSync) ) & (fsmcAddrSync(10,0) === 0.U) ){
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status := fsmcdataInSync
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statusReg := fsmcdataInSync
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}
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when( (~fsmcCEnSync & fsmcAddrSync.extract(12) & (~fsmcWEnSync) ) & (fsmcAddrSync(10,0) === 1.U) ){
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slvNum := fsmcdataInSync
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slvNumReg := fsmcdataInSync
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}
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}
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@@ -217,3 +220,5 @@ trait BackBoardMstLVDS{ this: BackBoardMstBase =>
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}
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class BackBoardMst extends BackBoardMstBase with BackBoardMstFSMC with BackBoardMstLVDS
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@@ -32,12 +32,12 @@ abstract class BackBoardSlvBase extends RawModule{
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lvdsSlv.io.lvds_down_din := io.lvds_down_din
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lvdsSlv.io.lvds_down_dout := io.lvds_down_dout
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io.lvds_down_dout := lvdsSlv.io.lvds_down_dout
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lvdsSlv.io.lvds_up_din := io.lvds_up_din
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lvdsSlv.io.lvds_up_dout := io.lvds_up_dout
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io.lvds_up_dout := lvdsSlv.io.lvds_up_dout
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val downReg = Reg(Vec(32, UInt(8.W)))
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val upReg = Reg(Vec(32, UInt(8.W)))
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val downRegWire = Wire(Vec(32, UInt(8.W)))
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val upRegWire = Wire(Vec(32, UInt(8.W)))
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@@ -50,8 +50,8 @@ abstract class BackBoardSlvBase extends RawModule{
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// val downstream_rx_cdr_err = Output(Bool())
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// val downstream_sync = Output(Bool())
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val upstream_tx_data_ready = Output(Bool())
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val upstream_tx_data_in = Input(UInt(8.W))
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// val upstream_tx_data_ready = Output(Bool())
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// val upstream_tx_data_in = Input(UInt(8.W))
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// val upstream_rx_crc_valid = Output(Bool())
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// val upstream_rx_crc_err = Output(Bool())
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@@ -63,9 +63,13 @@ abstract class BackBoardSlvBase extends RawModule{
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trait BackBoardSlvDown{ this: BackBoardSlvBase =>
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withClockAndReset( io.ides_pclk.asClock, io.reset ){
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val downReg = Reg(Vec(32, UInt(8.W))); downRegWire := downReg
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val downCnt = RegInit(0.U(6.W))
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val downTimeoutEn = RegInit( false.B )
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val downTimeoutRst = (downCnt === 0.U & downstream_rx_data_valid)
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val downTimeoutRst = (downCnt === 0.U & lvdsSlv.io.downstream_rx_data_valid)
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val ( _, downTimeout ) = Counter( Range( 0,1023 ), downTimeoutEn, downTimeoutRst )
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@@ -74,8 +78,8 @@ trait BackBoardSlvDown{ this: BackBoardSlvBase =>
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downReg(i) := 0.U
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}
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} .otherwise{
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when( downstream_rx_data_valid ){
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downReg(downCnt) := downstream_rx_data_out
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when( lvdsSlv.io.downstream_rx_data_valid ){
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downReg(downCnt) := lvdsSlv.io.downstream_rx_data_out
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}
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}
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@@ -83,7 +87,7 @@ trait BackBoardSlvDown{ this: BackBoardSlvBase =>
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downTimeoutEn := false.B
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} .elsewhen( downCnt === 32.U ){
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downTimeoutEn := false.B
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} .elsewhen(downCnt === 0.U & downstream_rx_data_valid){
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} .elsewhen(downCnt === 0.U & lvdsSlv.io.downstream_rx_data_valid){
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downTimeoutEn := true.B
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}
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@@ -91,7 +95,7 @@ trait BackBoardSlvDown{ this: BackBoardSlvBase =>
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downCnt := 0.U
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}.elsewhen( downCnt === 32.U ){
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downCnt := 0.U
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}.elsewhen( downstream_rx_data_valid ){
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}.elsewhen( lvdsSlv.io.downstream_rx_data_valid ){
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downCnt := downCnt + 1.U
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}
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@@ -103,16 +107,18 @@ trait BackBoardSlvUp{ this: BackBoardSlvBase =>
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withClockAndReset( io.ides_pclk.asClock, io.reset ){
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val upCnt = RegInit(0.U(6.W))
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val upTimeoutEn = RegInit( false.B )
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val upTimeoutRst = (upCnt === 0.U & upstream_tx_data_ready)
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val upTimeoutRst = (upCnt === 0.U & lvdsSlv.io.upstream_tx_data_ready)
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val ( _, upTimeout ) = Counter( Range( 0,1023 ), upTimeoutEn, upTimeoutRst )
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lvdsSlv.io.upstream_tx_data_in := upRegWire(upCnt)
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// when( upstream_tx_data_ready ){
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// upstream_tx_data_ready := upReg(upCnt)
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// upstream_tx_data_ready := upRegWire(upCnt)
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// }
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when( io.reset ){
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for( i <- 0 until 32 ){
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upReg(i) := 0.U
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upRegWire(i) := 0.U
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}
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} .otherwise{
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@@ -122,18 +128,20 @@ trait BackBoardSlvUp{ this: BackBoardSlvBase =>
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upTimeoutEn := false.B
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} .elsewhen( upCnt === 32.U ){
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upTimeoutEn := false.B
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} .elsewhen(upCnt === 0.U & upstream_tx_data_ready){
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} .elsewhen(upCnt === 32.U & lvdsSlv.io.upstream_tx_data_ready){
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upTimeoutEn := true.B
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}
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when( upTimeout ){
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upCnt := 0.U
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}.elsewhen( upCnt === 32.U ){
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}.elsewhen( upCnt === 32.U & lvdsSlv.io.upstream_tx_data_ready ){
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upCnt := 0.U
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}.elsewhen( upstream_tx_data_ready ){
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}.elsewhen( lvdsSlv.io.upstream_tx_data_ready ){
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upCnt := upCnt + 1.U
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}
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}
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}
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@@ -4,173 +4,193 @@ import chisel3._
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import chisel3.util._
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class BackBoardSlvDigitalIO extends BackBoardSlvBase with BackBoardSlvDown with BackBoardSlvUp{
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val in = IO(Input(UInt(32.W)))
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val out = IO(Output(UInt(32.W)))
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val oe = IO(Output(UInt(32.W)))
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withClockAndReset( io.ides_pclk.asClock, io.reset ){
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val upReg = Reg(Vec(32, UInt(8.W))); upRegWire := upReg
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out := Cat( (0 until 4).map{i => downRegWire(i)}.reverse )
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oe := Cat( (4 until 8).map{i => downRegWire(i)}.reverse )
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trait LocalRegisters { this: BackBoardSlvBase =>
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val led = IO(Output(UInt(3.W)))
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val sw = IO( Input(UInt(1.W)))
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val digitalDir = RegInit(0.U(32.W))
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val digitalOut = RegInit(0.U(32.W))
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val digitalIn = RegInit(VecInit(Seq.fill(32){false.B}))
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val digitalFilter = RegInit(0.U(2.W))
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val clk100usCnt = RegInit(0.U(13.W))
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when( clk100usCnt < 5000.U ){
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clk100usCnt := clk100usCnt + 1.U
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} .otherwise{
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clk100usCnt := 0.U
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}
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for( i <- 0 until 32 ) {
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val hiCnt = RegInit( 0.U( 7.W ) )
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val loCnt = RegInit( 0.U( 7.W ) )
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val toCnt = RegInit( 0.U( 7.W ) )
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when( digitalFilter === "b00".U ){
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digitalIn(i) := sw
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} .elsewhen( digitalFilter === "b01".U ){
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when( clk100usCnt === 5000.U ){
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when( toCnt === 10.U ){
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hiCnt := 0.U
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loCnt := 0.U
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toCnt := 0.U
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when( hiCnt >= 8.U & digitalIn(i) === false.B){ digitalIn(i) := true.B }
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when( loCnt >= 8.U & digitalIn(i) === true.B) { digitalIn(i) := false.B }
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} .elsewhen( toCnt > 10.U ){
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hiCnt := 0.U
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loCnt := 0.U
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toCnt := 0.U
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} .otherwise{
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when(sw === true.B) { hiCnt := hiCnt + 1.U }
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when(sw === false.B) { loCnt := loCnt + 1.U }
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toCnt := toCnt + 1.U
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}
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}
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} .elsewhen( digitalFilter === "b10".U ){
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when( clk100usCnt === 5000.U ){
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when( toCnt === 40.U ){
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hiCnt := 0.U
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loCnt := 0.U
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toCnt := 0.U
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when( hiCnt >= 32.U & digitalIn(i) === false.B){ digitalIn(i) := true.B }
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when( loCnt >= 32.U & digitalIn(i) === true.B) { digitalIn(i) := false.B }
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} .elsewhen( toCnt > 40.U ){
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hiCnt := 0.U
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loCnt := 0.U
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toCnt := 0.U
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} .otherwise{
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when(sw === true.B) { hiCnt := hiCnt + 1.U }
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when(sw === false.B) { loCnt := loCnt + 1.U }
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toCnt := toCnt + 1.U
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}
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}
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} .elsewhen( digitalFilter === "b11".U ){
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when( clk100usCnt === 5000.U ){
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when( toCnt === 80.U ){
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hiCnt := 0.U
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loCnt := 0.U
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toCnt := 0.U
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when( hiCnt >= 64.U & digitalIn(i) === false.B){ digitalIn(i) := true.B }
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when( loCnt >= 64.U & digitalIn(i) === true.B) { digitalIn(i) := false.B }
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} .elsewhen( toCnt > 80.U ){
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hiCnt := 0.U
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loCnt := 0.U
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toCnt := 0.U
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} .otherwise{
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when(sw === true.B) { hiCnt := hiCnt + 1.U }
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when(sw === false.B) { loCnt := loCnt + 1.U }
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toCnt := toCnt + 1.U
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}
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when( true.B ){
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for( i <- 0 until 4 ) {
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upReg(i) := in( i*8+7,8*i )
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}
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}
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}
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}
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// trait LocalRegisters { this: BackBoardSlvBase =>
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// val led = IO(Output(UInt(3.W)))
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// val sw = IO( Input(UInt(1.W)))
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// val digitalDir = RegInit(0.U(32.W))
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// val digitalOut = RegInit(0.U(32.W))
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// val digitalIn = RegInit(VecInit(Seq.fill(32){false.B}))
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// val digitalFilter = RegInit(0.U(2.W))
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// val clk100usCnt = RegInit(0.U(13.W))
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// when( clk100usCnt < 5000.U ){
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// clk100usCnt := clk100usCnt + 1.U
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// } .otherwise{
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// clk100usCnt := 0.U
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// }
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// for( i <- 0 until 32 ) {
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// val hiCnt = RegInit( 0.U( 7.W ) )
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// val loCnt = RegInit( 0.U( 7.W ) )
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// val toCnt = RegInit( 0.U( 7.W ) )
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// when( digitalFilter === "b00".U ){
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// digitalIn(i) := sw
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// } .elsewhen( digitalFilter === "b01".U ){
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// when( clk100usCnt === 5000.U ){
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// when( toCnt === 10.U ){
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// hiCnt := 0.U
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// loCnt := 0.U
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// toCnt := 0.U
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// when( hiCnt >= 8.U & digitalIn(i) === false.B){ digitalIn(i) := true.B }
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// when( loCnt >= 8.U & digitalIn(i) === true.B) { digitalIn(i) := false.B }
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// } .elsewhen( toCnt > 10.U ){
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// hiCnt := 0.U
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// loCnt := 0.U
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// toCnt := 0.U
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// } .otherwise{
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// when(sw === true.B) { hiCnt := hiCnt + 1.U }
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// when(sw === false.B) { loCnt := loCnt + 1.U }
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// toCnt := toCnt + 1.U
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// }
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// }
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// } .elsewhen( digitalFilter === "b10".U ){
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// when( clk100usCnt === 5000.U ){
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// when( toCnt === 40.U ){
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// hiCnt := 0.U
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// loCnt := 0.U
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// toCnt := 0.U
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// when( hiCnt >= 32.U & digitalIn(i) === false.B){ digitalIn(i) := true.B }
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// when( loCnt >= 32.U & digitalIn(i) === true.B) { digitalIn(i) := false.B }
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// } .elsewhen( toCnt > 40.U ){
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// hiCnt := 0.U
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// loCnt := 0.U
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// toCnt := 0.U
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// } .otherwise{
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// when(sw === true.B) { hiCnt := hiCnt + 1.U }
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// when(sw === false.B) { loCnt := loCnt + 1.U }
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// toCnt := toCnt + 1.U
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// }
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// }
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// } .elsewhen( digitalFilter === "b11".U ){
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// when( clk100usCnt === 5000.U ){
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// when( toCnt === 80.U ){
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// hiCnt := 0.U
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// loCnt := 0.U
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// toCnt := 0.U
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// when( hiCnt >= 64.U & digitalIn(i) === false.B){ digitalIn(i) := true.B }
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// when( loCnt >= 64.U & digitalIn(i) === true.B) { digitalIn(i) := false.B }
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// } .elsewhen( toCnt > 80.U ){
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// hiCnt := 0.U
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// loCnt := 0.U
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// toCnt := 0.U
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// } .otherwise{
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// when(sw === true.B) { hiCnt := hiCnt + 1.U }
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// when(sw === false.B) { loCnt := loCnt + 1.U }
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// toCnt := toCnt + 1.U
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// }
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// }
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// }
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// }
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|
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|
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|
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val pluseCnt = RegInit(0.U(32.W))
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// val pluseCnt = RegInit(0.U(32.W))
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val pluseShift = ShiftRegisters( sw, 3, false.B, true.B )
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when( ~pluseShift(2).asBool & pluseShift(1).asBool ){
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pluseCnt := pluseCnt + 1.U
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}
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// val pluseShift = ShiftRegisters( sw, 3, false.B, true.B )
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// when( ~pluseShift(2).asBool & pluseShift(1).asBool ){
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// pluseCnt := pluseCnt + 1.U
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// }
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val pluseAutoCnt = RegInit(0.U(32.W))
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val pluseAutoFre = RegInit(0.U(32.W))
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when( clk100usCnt === 5000.U ){
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pluseAutoCnt := 0.U
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pluseAutoFre := pluseAutoCnt
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} .elsewhen( ~pluseShift(2).asBool & pluseShift(1).asBool ){
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pluseAutoCnt := pluseAutoCnt + 1.U
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}
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// val pluseAutoCnt = RegInit(0.U(32.W))
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// val pluseAutoFre = RegInit(0.U(32.W))
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// when( clk100usCnt === 5000.U ){
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// pluseAutoCnt := 0.U
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// pluseAutoFre := pluseAutoCnt
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// } .elsewhen( ~pluseShift(2).asBool & pluseShift(1).asBool ){
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// pluseAutoCnt := pluseAutoCnt + 1.U
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// }
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val qeiA = IO(Input(Bool()))
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val qeiB = IO(Input(Bool()))
|
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// val qeiA = IO(Input(Bool()))
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// val qeiB = IO(Input(Bool()))
|
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|
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val qeiAShift = ShiftRegisters( qeiA, 2, false.B, true.B )
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val qeiBShift = ShiftRegisters( qeiB, 3, false.B, true.B )
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// val qeiAShift = ShiftRegisters( qeiA, 2, false.B, true.B )
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// val qeiBShift = ShiftRegisters( qeiB, 3, false.B, true.B )
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val qeiCnt = RegInit(0.U(32.W))
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val qeiAutoCnt = RegInit(0.U(32.W))
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val qeiAutoFre = RegInit(0.U(32.W))
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// val qeiCnt = RegInit(0.U(32.W))
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||||
// val qeiAutoCnt = RegInit(0.U(32.W))
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// val qeiAutoFre = RegInit(0.U(32.W))
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||||
|
||||
when( ~qeiBShift(2) & qeiBShift(1) ){
|
||||
qeiCnt := Mux( qeiAShift(1), qeiCnt + 1.U, qeiCnt - 1.U )
|
||||
qeiAutoCnt := Mux( qeiAShift(1), qeiCnt + 1.U, qeiCnt - 1.U )
|
||||
}
|
||||
// when( ~qeiBShift(2) & qeiBShift(1) ){
|
||||
// qeiCnt := Mux( qeiAShift(1), qeiCnt + 1.U, qeiCnt - 1.U )
|
||||
// qeiAutoCnt := Mux( qeiAShift(1), qeiCnt + 1.U, qeiCnt - 1.U )
|
||||
// }
|
||||
|
||||
|
||||
when( clk100usCnt === 5000.U ){
|
||||
qeiAutoCnt := 0.U
|
||||
qeiAutoFre := qeiAutoCnt
|
||||
} .elsewhen( ~qeiBShift(2) & qeiBShift(1) ){
|
||||
qeiAutoCnt := Mux( qeiAShift(1), qeiAutoCnt + 1.U, qeiAutoCnt - 1.U )
|
||||
}
|
||||
// when( clk100usCnt === 5000.U ){
|
||||
// qeiAutoCnt := 0.U
|
||||
// qeiAutoFre := qeiAutoCnt
|
||||
// } .elsewhen( ~qeiBShift(2) & qeiBShift(1) ){
|
||||
// qeiAutoCnt := Mux( qeiAShift(1), qeiAutoCnt + 1.U, qeiAutoCnt - 1.U )
|
||||
// }
|
||||
|
||||
|
||||
registersRD := Mux1H(Seq(
|
||||
(upStreamReq.io.latDat.bits.register === 0.U) -> digitalDir,
|
||||
(upStreamReq.io.latDat.bits.register === 1.U) -> digitalIn.asUInt,
|
||||
(upStreamReq.io.latDat.bits.register === 2.U) -> digitalFilter,
|
||||
(upStreamReq.io.latDat.bits.register === 3.U) -> pluseCnt,
|
||||
(upStreamReq.io.latDat.bits.register === 4.U) -> pluseAutoFre,
|
||||
(upStreamReq.io.latDat.bits.register === 5.U) -> qeiCnt,
|
||||
(upStreamReq.io.latDat.bits.register === 6.U) -> qeiAutoFre,
|
||||
))
|
||||
// registersRD := Mux1H(Seq(
|
||||
// (upStreamReq.io.latDat.bits.register === 0.U) -> digitalDir,
|
||||
// (upStreamReq.io.latDat.bits.register === 1.U) -> digitalIn.asUInt,
|
||||
// (upStreamReq.io.latDat.bits.register === 2.U) -> digitalFilter,
|
||||
// (upStreamReq.io.latDat.bits.register === 3.U) -> pluseCnt,
|
||||
// (upStreamReq.io.latDat.bits.register === 4.U) -> pluseAutoFre,
|
||||
// (upStreamReq.io.latDat.bits.register === 5.U) -> qeiCnt,
|
||||
// (upStreamReq.io.latDat.bits.register === 6.U) -> qeiAutoFre,
|
||||
// ))
|
||||
|
||||
when( upStreamReq.io.latDat.fire & upStreamReq.io.latDat.bits.address(5,1) === io.localHost & upStreamReq.io.latDat.bits.address.extract(0) === 1.U ){
|
||||
when(upStreamReq.io.latDat.bits.register === 0.U){
|
||||
digitalDir := upStreamReq.io.latDat.bits.data
|
||||
}
|
||||
when(upStreamReq.io.latDat.bits.register === 1.U){
|
||||
digitalOut := upStreamReq.io.latDat.bits.data
|
||||
}
|
||||
when(upStreamReq.io.latDat.bits.register === 2.U){
|
||||
digitalFilter := upStreamReq.io.latDat.bits.data
|
||||
}
|
||||
when(upStreamReq.io.latDat.bits.register === 3.U){
|
||||
pluseCnt := upStreamReq.io.latDat.bits.data
|
||||
}
|
||||
when(upStreamReq.io.latDat.bits.register === 4.U){
|
||||
;
|
||||
}
|
||||
when(upStreamReq.io.latDat.bits.register === 5.U){
|
||||
qeiCnt := upStreamReq.io.latDat.bits.data
|
||||
}
|
||||
when(upStreamReq.io.latDat.bits.register === 6.U){
|
||||
;
|
||||
}
|
||||
}
|
||||
// when( upStreamReq.io.latDat.fire & upStreamReq.io.latDat.bits.address(5,1) === io.localHost & upStreamReq.io.latDat.bits.address.extract(0) === 1.U ){
|
||||
// when(upStreamReq.io.latDat.bits.register === 0.U){
|
||||
// digitalDir := upStreamReq.io.latDat.bits.data
|
||||
// }
|
||||
// when(upStreamReq.io.latDat.bits.register === 1.U){
|
||||
// digitalOut := upStreamReq.io.latDat.bits.data
|
||||
// }
|
||||
// when(upStreamReq.io.latDat.bits.register === 2.U){
|
||||
// digitalFilter := upStreamReq.io.latDat.bits.data
|
||||
// }
|
||||
// when(upStreamReq.io.latDat.bits.register === 3.U){
|
||||
// pluseCnt := upStreamReq.io.latDat.bits.data
|
||||
// }
|
||||
// when(upStreamReq.io.latDat.bits.register === 4.U){
|
||||
// ;
|
||||
// }
|
||||
// when(upStreamReq.io.latDat.bits.register === 5.U){
|
||||
// qeiCnt := upStreamReq.io.latDat.bits.data
|
||||
// }
|
||||
// when(upStreamReq.io.latDat.bits.register === 6.U){
|
||||
// ;
|
||||
// }
|
||||
// }
|
||||
|
||||
|
||||
|
||||
|
||||
led := digitalOut(2,0)
|
||||
// digitalIn := sw
|
||||
}
|
||||
// led := digitalOut(2,0)
|
||||
// // digitalIn := sw
|
||||
// }
|
||||
@@ -17,12 +17,12 @@ object testModule extends App {
|
||||
))
|
||||
|
||||
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
|
||||
ChiselGeneratorAnnotation(() => { new BackBoardSlv })
|
||||
ChiselGeneratorAnnotation(() => { new BackBoardSlvDigitalIO })
|
||||
))
|
||||
|
||||
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
|
||||
ChiselGeneratorAnnotation(() => { new BackPlaneChainTest })
|
||||
))
|
||||
// (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
|
||||
// ChiselGeneratorAnnotation(() => { new BackPlaneChainTest })
|
||||
// ))
|
||||
|
||||
// val cfg = new MacCfg
|
||||
|
||||
|
||||
Reference in New Issue
Block a user