fix sram

2023-08-21 14:52:21 +08:00
parent 5f15e94ae3
commit 37ac7817d7
1 changed files with 1 additions and 2 deletions
--- a/src/main/scala/backBoard/MirrorSRAM.scala
+++ b/src/main/scala/backBoard/MirrorSRAM.scala
@@ -47,7 +47,7 @@ class MirrorSRAM extends BlackBox with HasBlackBoxInline {

  val io: MirrorSRAMIO = IO(new MirrorSRAMIO)

-  setInline("lvds_bus_master.v",
+  setInline("microSRAM.v",
              """
  |   module MirrorSRAM(
  |      output [7:0] datar,
@@ -86,7 +86,6 @@ class MirrorSRAM extends BlackBox with HasBlackBoxInline {
  |  defparam bram_sdpb_0.BIT_WIDTH_1 = 8;
  |  defparam bram_sdpb_0.RESET_MODE = "SYNC";
  |
-  | );
  |endmodule
    """.stripMargin)
 }