From 37ac7817d793fa6f37fd9166f19b57848b9c3e75 Mon Sep 17 00:00:00 2001
From: "Ruige Lee (WSL)" <295054118@whut.edu.cn>
Date: Mon, 21 Aug 2023 14:52:21 +0800
Subject: [PATCH] fix sram

---
 src/main/scala/backBoard/MirrorSRAM.scala | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/main/scala/backBoard/MirrorSRAM.scala b/src/main/scala/backBoard/MirrorSRAM.scala
index 89941a7..b7d808f 100644
--- a/src/main/scala/backBoard/MirrorSRAM.scala
+++ b/src/main/scala/backBoard/MirrorSRAM.scala
@@ -47,7 +47,7 @@ class MirrorSRAM extends BlackBox with HasBlackBoxInline {
 
   val io: MirrorSRAMIO = IO(new MirrorSRAMIO)
 
-  setInline("lvds_bus_master.v",
+  setInline("microSRAM.v",
               """
   |   module MirrorSRAM(
   |      output [7:0] datar,
@@ -86,7 +86,6 @@ class MirrorSRAM extends BlackBox with HasBlackBoxInline {
   |  defparam bram_sdpb_0.BIT_WIDTH_1 = 8;
   |  defparam bram_sdpb_0.RESET_MODE = "SYNC";
   |
-  | );
   |endmodule
     """.stripMargin)
 }