ruige/eb001
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

要求所有tx/rx时钟域异步复位

Browse Source
This commit is contained in:
RuigeLee
2023-09-25 14:18:27 +08:00
parent 5ff118f527
commit 51c39369c8
9 changed files with 45 additions and 43 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
rocket-chip

Submodule rocket-chip updated: 47f7b71447...15e7cfb7b7

26
src/main/scala/mac/MAC.scala
View File

@@ -69,6 +69,7 @@ class MacIO extends Bundle with MDIO{
// val int_o = Output(Bool())
val isLoopBack = Output(Bool())
val asyncReset = Input(AsyncReset())
}
class MacImp(outer: Mac)(implicit p: Parameters) extends LazyModuleImp(outer) with HasMacParameters{
@@ -439,8 +440,8 @@ val maccontrol = Module(new MacControl)
maccontrol.io.MTxClk := io.mtx_clk_pad_i
maccontrol.io.MRxClk := io.mrx_clk_pad_i
maccontrol.io.TxReset := reset.asBool
maccontrol.io.RxReset := reset.asBool
maccontrol.io.asyncReset := io.asyncReset
maccontrol.io.TPauseRq := TPauseRq
maccontrol.io.TxDataIn := TxData
maccontrol.io.TxStartFrmIn := TxStartFrm
@@ -507,9 +508,8 @@ MRxErr_Lb := Mux(r_LoopBck, io.mtxerr_pad_o, io.mrxerr_pad_i & RxEnSync)
MRxD_Lb := Mux(r_LoopBck, io.mtxd_pad_o, io.mrxd_pad_i)
val txethmac = Module(new MacTx)
txethmac.clock := io.mtx_clk_pad_i.asClock
txethmac.reset := reset.asBool
val txethmac = withClockAndReset(io.mtx_clk_pad_i.asClock, io.asyncReset)( Module(new MacTx))
txethmac.io.TxStartFrm := TxStartFrmOut
txethmac.io.TxEndFrm := TxEndFrmOut
txethmac.io.TxUnderRun := TxUnderRun
@@ -576,9 +576,8 @@ dontTouch(RxStateSFD )
dontTouch(RxStateData )
dontTouch(AddressMiss )
val rxethmac = Module(new MacRx)
rxethmac.clock := io.mrx_clk_pad_i.asClock
rxethmac.reset := reset.asBool
val rxethmac = withClockAndReset(io.mrx_clk_pad_i.asClock, io.asyncReset)( Module(new MacRx))
rxethmac.io.MRxDV := MRxDV_Lb
rxethmac.io.MRxD := MRxD_Lb
rxethmac.io.Transmitting := Transmitting
@@ -611,7 +610,7 @@ val rxethmac = Module(new MacRx)
AddressMiss := rxethmac.io.AddressMiss
withClockAndReset( io.mtx_clk_pad_i.asClock, reset ) {
withClockAndReset( io.mtx_clk_pad_i.asClock, reset.asAsyncReset ) {
// MII Carrier Sense Synchronization
CarrierSense_Tx2 := ShiftRegister(io.mcrs_pad_i, 2, false.B, true.B)
@@ -635,7 +634,7 @@ val rxethmac = Module(new MacRx)
withClockAndReset( io.mrx_clk_pad_i.asClock, reset ) {
withClockAndReset( io.mrx_clk_pad_i.asClock, reset.asAsyncReset ) {
val WillTransmit_q = ShiftRegister(WillTransmit, 2, false.B, true.B)
Transmitting := ~r_FullD & WillTransmit_q
@@ -653,7 +652,7 @@ val rxethmac = Module(new MacRx)
}
withClockAndReset( io.mtx_clk_pad_i.asClock, reset ) {
withClockAndReset( io.mtx_clk_pad_i.asClock, reset.asAsyncReset ) {
val TxPauseRq_sync = ShiftRegisters((r_TxPauseRq & r_TxFlow), 3, false.B, true.B )
TPauseRq := RegNext( TxPauseRq_sync(1) & (~TxPauseRq_sync(2)), false.B )
@@ -667,7 +666,7 @@ val rxethmac = Module(new MacRx)
val RxAbort_latch_wire = Wire(Bool())
val RxAbort_wb = ShiftRegister( RxAbort_latch_wire, 2, false.B, true.B )
withClockAndReset( io.mrx_clk_pad_i.asClock, reset ) {
withClockAndReset( io.mrx_clk_pad_i.asClock, reset.asAsyncReset ) {
val RxAbort_latch = RegInit(false.B); RxAbort_latch_wire := RxAbort_latch
val RxAbortRst = ShiftRegister( RxAbort_wb, 2, false.B, true.B )
@@ -684,6 +683,7 @@ val rxethmac = Module(new MacRx)
val wishbone = Module(new MacTileLink(slv_edge, mst_edge))
wishbone.io.asyncReset := io.asyncReset
wishbone.io.tlSlv.A.valid := slv_bus.a.valid
wishbone.io.tlSlv.A.bits := slv_bus.a.bits
@@ -759,7 +759,7 @@ val rxethmac = Module(new MacRx)
val macstatus = Module(new MacStatus)
macstatus.io.reset := reset.asBool
macstatus.io.asyncReset := io.asyncReset
macstatus.io.MRxClk := io.mrx_clk_pad_i
macstatus.io.RxCrcError := RxCrcError
macstatus.io.MRxErr := MRxErr_Lb

13
src/main/scala/mac/MacControl.scala
View File

@@ -6,8 +6,9 @@ import chisel3.util._
class MacControlIO extends Bundle{
val MTxClk = Input(Bool()) // Transmit clock (from PHY)
val MRxClk = Input(Bool()) // Receive clock (from PHY)
val TxReset = Input(Bool()) // Transmit reset
val RxReset = Input(Bool()) // Receive reset
val asyncReset = Input(AsyncReset())
val TPauseRq = Input(Bool()) // Transmit control frame (from host)
val TxDataIn = Input(UInt(8.W)) // Transmit packet data byte (from host)
val TxStartFrmIn = Input(Bool()) // Transmit packet start frame input (from host)
@@ -96,7 +97,7 @@ class MacControl extends RawModule{
withClockAndReset( io.MTxClk.asClock, io.TxReset ) {
withClockAndReset( io.MTxClk.asClock, io.asyncReset ) {
val BlockTxDone = RegInit(false.B)
val SendingCtrlFrm = RegInit(false.B) // Sending Control Frame (enables padding and CRC)
val CtrlMux = RegInit(false.B)
@@ -193,7 +194,7 @@ class MacControl extends RawModule{
}
val IncrementDlyCrcCnt = CtrlMux & io.TxUsedDataIn & ~DlyCrcCnt.extract(2)
val ResetByteCnt = io.TxReset | (~TxCtrlStartFrm & (io.TxDoneIn | io.TxAbortIn))
val ResetByteCnt = io.asyncReset.asBool | (~TxCtrlStartFrm & (io.TxDoneIn | io.TxAbortIn))
// Delayed CRC counter
when(ResetByteCnt){
@@ -277,7 +278,7 @@ class MacControl extends RawModule{
withClockAndReset( io.MRxClk.asClock, io.RxReset ) {
withClockAndReset( io.MRxClk.asClock, io.asyncReset.asAsyncReset ) {
val AddressOK = RegInit(false.B); io.ControlFrmAddressOK := AddressOK // Multicast or unicast address detected
val TypeLengthOK = RegInit(false.B) // Type/Length field contains 0x8808
val DetectionWindow = RegInit(true.B) // Detection of the PAUSE frame is possible within this window
@@ -411,7 +412,7 @@ class MacControl extends RawModule{
val SlotTimer = RegInit(0.U(6.W)) // SlotTimer
when(io.RxReset){
when(io.asyncReset.asBool()){
SlotTimer := 0.U
} .elsewhen(Pause_wire & io.RxFlow & Divider2){
SlotTimer := SlotTimer + 1.U

5
src/main/scala/mac/MacRegisters.scala
View File

@@ -72,6 +72,7 @@ class MacRegIO extends Bundle{
val r_TxPauseTV = Output(UInt(16.W))
val r_TxPauseRq = Output(Bool())
val asyncReset = Input(AsyncReset())
}
class MacReg(implicit p: Parameters) extends LazyModule{
@@ -417,7 +418,7 @@ class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(out
withClockAndReset( io.TxClk.asClock, reset ) {
withClockAndReset( io.TxClk.asClock, io.asyncReset ) {
// val ResetTxCIrq_sync1 = Reg(Bool())
val ResetTxCIrq_sync2 = RegNext(SetTxCIrq_sync1, false.B)
val SetTxCIrq_txclk = RegInit(false.B); SetTxCIrq_txclk_wire := SetTxCIrq_txclk
@@ -432,7 +433,7 @@ class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(out
}
withClockAndReset( io.RxClk.asClock, reset ) {
withClockAndReset( io.RxClk.asClock, io.asyncReset ) {
val ResetRxCIrq_sync1 = RegNext(SetRxCIrq_sync2, false.B)
val ResetRxCIrq_sync2 = RegNext(ResetRxCIrq_sync1, false.B)
val ResetRxCIrq_sync3 = RegNext(ResetRxCIrq_sync2, false.B)

2
src/main/scala/mac/MacRx.scala
View File

@@ -40,7 +40,7 @@ class MacRxIO extends Bundle{
}
abstract class MacRxBase extends Module{
abstract class MacRxBase extends Module with RequireAsyncReset{
val io: MacRxIO = IO(new MacRxIO)
val MRxDEqD = io.MRxD === "hd".U

6
src/main/scala/mac/MacStatus.scala
View File

@@ -4,7 +4,7 @@ import chisel3._
import chisel3.util._
class MacStatusIO extends Bundle{
val reset = Input(Bool())
val asyncReset = Input(AsyncReset())
val MRxClk = Input(Bool())
val RxCrcError = Input(Bool())
@@ -63,7 +63,7 @@ class MacStatusIO extends Bundle{
class MacStatus extends RawModule{
val io: MacStatusIO = IO(new MacStatusIO)
withClockAndReset( io.MRxClk.asClock, io.reset ) {
withClockAndReset( io.MRxClk.asClock, io.asyncReset ) {
val LatchedCrcError = RegInit(false.B); io.LatchedCrcError := LatchedCrcError // Crc error
@@ -149,7 +149,7 @@ class MacStatus extends RawModule{
withClockAndReset( io.MTxClk.asClock, io.reset ) {
withClockAndReset( io.MTxClk.asClock, io.asyncReset ) {
val RetryCntLatched = RegEnable( io.RetryCnt, 0.U(4.W), io.StartTxDone | io.StartTxAbort); io.RetryCntLatched := RetryCntLatched
val RetryLimit = RegEnable( io.MaxCollisionOccured, false.B, io.StartTxDone | io.StartTxAbort ); io.RetryLimit := RetryLimit // Latched Retransmission limit
val LateCollLatched = RegEnable( io.LateCollision, false.B, io.StartTxDone | io.StartTxAbort); io.LateCollLatched := LateCollLatched // Latched Late Collision

6
src/main/scala/mac/MacTilelink.scala
View File

@@ -88,7 +88,7 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
val RxE_IRQ = Output(Bool())
val Busy_IRQ = Output(Bool())
val asyncReset = Input(AsyncReset())
}
@@ -1140,7 +1140,7 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
trait MacTileLinkTXClk{ this: MacTileLinkBase =>
withClockAndReset( io.MTxClk.asClock, reset.asAsyncReset ) {
withClockAndReset( io.MTxClk.asClock, io.asyncReset ) {
val Flop = RegInit(false.B)
// Synchronizing BlockingTxStatusWrite to MTxClk
@@ -1313,7 +1313,7 @@ trait MacTileLinkTXClk{ this: MacTileLinkBase =>
trait MacTileLinkRXClk{ this: MacTileLinkBase =>
withClockAndReset( io.MRxClk.asClock, reset.asAsyncReset ){
withClockAndReset( io.MRxClk.asClock, io.asyncReset ){
val RxDataLatched2 = RegInit(0.U(32.W)); RxDataLatched2_rxclk := RxDataLatched2
val RxDataLatched1 = RegInit(0.U(24.W)) // Little Endian Byte Ordering[23:0]

2
src/main/scala/mac/MacTx.scala
View File

@@ -46,7 +46,7 @@ class MacTxIO extends Bundle{
val StateData = Output(UInt(2.W))
}
abstract class MacTxBase extends Module{
abstract class MacTxBase extends Module with RequireAsyncReset{
val io: MacTxIO = IO(new MacTxIO)

26
src/test/scala/gcd/test.scala
View File

@@ -12,26 +12,26 @@ import org.chipsalliance.cde.config._
object testModule extends App {
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
ChiselGeneratorAnnotation(() => { new BackBoardMst }),
))
// (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
// ChiselGeneratorAnnotation(() => { new BackBoardMst }),
// ))
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
ChiselGeneratorAnnotation(() => { new BackBoardSlvDigitalIO })
))
// (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
// ChiselGeneratorAnnotation(() => { new BackBoardSlvDigitalIO })
// ))
// (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
// ChiselGeneratorAnnotation(() => { new BackPlaneChainTest })
// ))
// val cfg = new MacCfg
val cfg = new MacCfg
// (new chisel3.stage.ChiselStage).execute( Array("--show-registrations", "--full-stacktrace", "--target-dir", "generated/Main") ++ args, Seq(
// ChiselGeneratorAnnotation(() => {
// val soc = LazyModule(new MacTest()(cfg))
// soc.module
// })
// ))
(new chisel3.stage.ChiselStage).execute( Array("--show-registrations", "--full-stacktrace", "--target-dir", "generated/Main", "-e", "verilog") ++ args, Seq(
ChiselGeneratorAnnotation(() => {
val soc = LazyModule(new MacTest()(cfg))
soc.module
})
))
}