增加rx功能buff,底座
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@@ -31,7 +31,11 @@ class RevBuffIO extends Bundle{
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}
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class Packet_Info_Bundle extends Bundle{
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val LatchedRxLength = UInt(16.W)
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val RxStatusInLatched = UInt(9.W)
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val header = Vec( 5, UInt(32.W) )
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}
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class RevBuff extends Module{
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@@ -41,12 +45,50 @@ class RevBuff extends Module{
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val isPong = ~isPing
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val pipoBuff = for( i <- 0 until 2 ) yiled { Module(new Queue( UInt(32.W), 2048/4 )) }
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val pipoInfo = for( i <- 0 until 2 ) yiled { Reg(Vec( 18, UInt(8.W))) }
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val pipoInfo = for( i <- 0 until 2 ) yiled { Reg(new Packet_Info_Bundle) }
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val recCnt = RegInit(0.U(5.W))
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val recCnt = RegInit(0.U(3.W))
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pipoBuff(0).io.enq.valid := isPing & io.enq.data.valid
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pipoBuff(0).io.enq.bits := io.enq.data.bits
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pipoBuff(1).io.enq.valid := isPong & io.enq.data.valid
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pipoBuff(1).io.enq.btis := io.enq.data.bits
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io.enq.data.ready := (isPing & io.enq.data.ready) | (isPong & io.enq.data.ready)
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io.enq.ctrl.ready := true.B
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pipoBuff(0).reset := reset.asBool | (isPing & io.enq.ctrl.fire & io.enq.ctrl.bits.isRxAbort)
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pipoBuff(1).reset := reset.asBool | (isPong & io.enq.ctrl.fire & io.enq.ctrl.bits.isRxAbort)
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when( io.enq.ctrl.fire & ~io.enq.ctrl.bits.isRxAbort){
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isPing := ~isPing
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when( isPing ){
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pipoInfo(0).LatchedRxLength := io.enq.ctrl.bits.LatchedRxLength
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pipoInfo(0).RxStatusInLatched := io.enq.ctrl.bits.RxStatusInLatched
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} .elsewhen( isPong ){
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pipoInfo(1).LatchedRxLength := io.enq.ctrl.bits.LatchedRxLength
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pipoInfo(1).RxStatusInLatched := io.enq.ctrl.bits.RxStatusInLatched
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}
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}
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when( io.enq.ctrl.fire ){
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recCnt := 0.U
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} .elsewhen( io.enq.data.fire ){
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when( recCnt < 5 ){
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recCnt := recCnt + 1.U
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when( isPing ){
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pipoInfo(0).header(recCnt) := io.enq.data.bits
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} .elsewhen( isPong ){
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pipoInfo(1).header(recCnt) := io.enq.data.bits
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} .otherwise{
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assert(false.B, "Assert Failed, Rx Under Run")
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}
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}
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}
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