eb001/src/main/scala/backBoard/shin/Interface.scala

package BACK

import chisel3._
import chisel3.util._




class Stat_IO_Bundle extends Bundle{
  val isHeaderError    = Bool()
  val isSubHeaderError = Bool()
  val isPayloadError   = Bool()
  val isSubTailError   = Bool()
  val isCRCError       = Bool()
  val isFinish         = Bool()
  val isRecByteAck     = Bool()

  def isRecError = isHeaderError | isSubHeaderError | isPayloadError | isSubTailError | isCRCError
}



class EBMMU_Bundle extends Bundle{
  val lAddr = UInt(30.W)
  val pAddr = UInt(16.W)
  val length = UInt(16.W)
  val op = UInt(8.W)
  val isEnable = Bool()

  def EBMMU_OP_RD = op === 1.U
  def EBMMU_OP_WR = op === 2.U
  def EBMMU_OP_RW = op === 3.U
}

class CommonRegisterBundle extends Bundle{
  val mstOrSlv  = UInt(2.W)
  def modeSel:Bool = mstOrSlv === "h1".U

  val hwVersion = UInt(8.W)
  val hwSerial  = UInt(48.W)
  val busRate   = UInt(8.W)

  val spiSel    = UInt(2.W)

  val softResetCode = Vec(4, UInt(8.W))

  val intEnable = UInt(32.W)
  val intStatus = UInt(32.W)
  val intMode   = UInt(16.W)



  val statDownRecErrorCnt          = UInt(32.W)
  val statDownRecHeaderErrorCnt    = UInt(16.W)
  val statDownRecSubHeaderErrorCnt = UInt(16.W)
  val statDownRecPayloadErrorCnt   = UInt(16.W)
  val statDownRecSubTailErrorCnt   = UInt(16.W)
  val statDownRecCRCErrorCnt       = UInt(16.W)
  val statDownRecFinishCnt         = UInt(32.W)
  val statDownRecByteCnt           = UInt(64.W)

  val statUpRecErrorCnt          = UInt(32.W)
  val statUpRecHeaderErrorCnt    = UInt(16.W)
  val statUpRecSubHeaderErrorCnt = UInt(16.W)
  val statUpRecPayloadErrorCnt   = UInt(16.W)
  val statUpRecSubTailErrorCnt   = UInt(16.W)
  val statUpRecCRCErrorCnt       = UInt(16.W)
  val statUpRecFinishCnt         = UInt(32.W)
  val statUpRecByteCnt           = UInt(64.W)




  val wdtStatus = UInt(32.W)
  val wdtEnable = UInt(32.W)
  val wdtTarCnt = Vec( 18, UInt(32.W) )

  val timeStamp = UInt(64.W)
  val mstDeltaTime = UInt(32.W)
  val syncCfg = UInt(8.W)
  val syncWidth  = Vec(4, UInt(16.W) )
  val syncOffset = Vec(4, UInt(32.W))
  val syncPoint = UInt(64.W)
  val syncPeroid = UInt(32.W)
  val recoTimeStamp = UInt(64.W) //时钟补偿寄存器

  val localPeroid = UInt(32.W)
  val localPoint  = UInt(64.W)


  val custom = Vec( 128, UInt(8.W) )

  val smUsedDepth = Vec(8, UInt(8.W))
  val smTrigLen = Vec(8, UInt(11.W))  //触发SM切换缓冲区的地址 （或读或写）

  val event = new Bundle{
    val latchCtl = Vec(2, UInt(4.W))
    val latchStatus = Vec(2, UInt(4.W))
    val posedgeTimeStampLatch = Vec(2, UInt(64.W))
    val negedgeTimeStampLatch = Vec(2, UInt(64.W))
    val mcuSMTimeStampEnq  = UInt(64.W)
    val mcuSMTimeStampDeq  = UInt(64.W)
    val lvdsSMTimeStampEnq = UInt(64.W)
    val lvdsSMTimeStampDeq = UInt(64.W)
  }
}

class MasterRegisterBundle extends Bundle{
  val txSM         = UInt(2.W)
  val rxSM         = UInt(2.W)

  val rplTimeStampTx = UInt(16.W)
}


class SlaveRegisterBundle extends Bundle{
  val ebmmu = Vec(16, new EBMMU_Bundle)

  val localDevIndex = UInt(16.W)

  //链路寄存器组

  val isDevOnRight = UInt(2.W)
  val isDevOnRightModify = Bool()
  val indexOfRightDev = UInt(14.W)


  val slvDeltaTime  = UInt(32.W) //从站时间戳差值
  val deltaFinal    = UInt(32.W) //当前时间戳与主站时间差




}



class InterfaceIO extends Bundle{
  val ospi = new SSPIInterfaceIO
  val oqspi = new QSPIInterfaceIO
  val iqspi = new QSPIInterfaceIO

  val lvds  = Flipped(new RegAccessInterfaceIO)

  val txReq = Valid(new Bundle{
    val txSM = UInt(2.W)
    val rxSM = UInt(2.W)
  }) //发送请求和SM代号


  val dSMdeq = Output( Vec(4, Bool()) )
  val uSMenq = Output( Vec(4, Bool()) )

  val lvdsSMEnq = Input(Vec(4, Bool()))
  val lvdsSMDeq = Input(Vec(4, Bool()))

  val sram_w = Flipped(Vec( 4, new SRAM2kWRIO)) //QSPI
  val sram_r = Flipped(Vec( 4, new SRAM2kRDIO)) //QSPI

  val cReg = Output(new CommonRegisterBundle)
  val mReg = Output(new MasterRegisterBundle)
  val sReg = Output(new SlaveRegisterBundle)

  val localDevIndex = Input(UInt(16.W))

  val isDevOnRight = Input(UInt(2.W))
  val isDevOnRightModify = Input(Bool())
  val indexOfRightDev = Input(UInt(14.W))



  val slvDeltaTime  = Input(UInt(32.W)) //从站时间戳差值
  val mstDeltaTime  = Input(UInt(32.W))
  val deltaFinal = Input(UInt(32.W))

  val sync = Output(Vec(4, Bool()))


  val isSoftReset = Output(Bool())
  val intMstTrig  = Input(Vec(2, Bool()))
  val intHWTrig   = Input(Vec(2, Bool()))
  val intHWClr    = Output(Vec(2, Bool()))
  val intSlvTrig  = Input(Vec(8, Bool()))
  val intTransEnd = Input(Vec(4,Bool()))

  val interrupt = Output(Bool())

  val wdtTrigger = Input(Vec(18, Bool()))

  val downRecStat = Input(new Stat_IO_Bundle)
  val upRecStat   = Input(new Stat_IO_Bundle)

  val smUsedDepth = Input( Vec(8, UInt(8.W)) )
  val isSMReset = Output( Vec(8, Bool()) )

  val latchPin = Input(Vec(2, Bool()))
  val isPoReset = Output(Bool())
}


abstract class InterfaceBase extends Module{
  val io: InterfaceIO = IO(new InterfaceIO)

  val oSpi  = Module(new SSpiInterface)
  val oQSpi = Module(new QSpiInterface)
  val iQSpi = Module(new QSpiInterface)

  io.ospi <> oSpi.spi
  io.oqspi <> oQSpi.qspi
  io.iqspi <> iQSpi.qspi

  val cReg = Wire(new CommonRegisterBundle); io.cReg := cReg
  val mReg = Wire(new MasterRegisterBundle); io.mReg := mReg
  val sReg = Wire(new SlaveRegisterBundle);  io.sReg := sReg






  val isSysInit = cReg.mstOrSlv =/= 0.U
  val isMstMode = cReg.mstOrSlv === "h1".U
  val isSlvMode = cReg.mstOrSlv === "h2".U

  def AcquireReg(addr: UInt): UInt = {
    Mux1H(
      Seq(
      (addr === "h0".U) -> cReg.mstOrSlv,
      (addr === "h1".U) -> cReg.hwVersion,
      ) ++

      ((0 until 6).map{ i =>
        (addr === ("h2".U(16.W) + i.U) ) -> cReg.hwSerial( 8*i+7,8*i+0 )
      }) ++
      
      Seq(
        (addr === "h8".U )  -> cReg.busRate( 7,0 ),
        (addr === "h9".U )  -> cReg.spiSel,
        (addr === "ha".U & isSlvMode)  -> sReg.localDevIndex(7,0),
        (addr === "hb".U & isSlvMode)  -> sReg.localDevIndex(15,8),


        (addr === "h20".U & isMstMode) -> Cat(mReg.rxSM, mReg.txSM, 0.U(1.W) ),
                //(addr === "h21".U & isMstMode) -> mReg.txLength,

        (addr === "h24".U & isMstMode) -> mReg.rplTimeStampTx(7,0),
        (addr === "h25".U & isMstMode) -> mReg.rplTimeStampTx(15,8),



      ) ++






      Seq(
        (addr === "h40".U ) -> cReg.softResetCode(1),
        (addr === "h41".U ) -> cReg.softResetCode(1),
        (addr === "h42".U ) -> cReg.softResetCode(2),
        (addr === "h43".U ) -> cReg.softResetCode(3),

        (addr === "h70".U ) -> cReg.intEnable(7,0),
        (addr === "h71".U ) -> cReg.intEnable(15,8),
        (addr === "h72".U ) -> cReg.intEnable(23,16),
        (addr === "h73".U ) -> cReg.intEnable(31,24),

        (addr === "h74".U ) -> cReg.intStatus(7,0),
        (addr === "h75".U ) -> cReg.intStatus(15,8),
        (addr === "h76".U ) -> cReg.intStatus(23,16),
        (addr === "h77".U ) -> cReg.intStatus(31,24),

        (addr === "h7c".U ) -> cReg.intMode(7,0),
        (addr === "h7d".U ) -> cReg.intMode(15,8),


        (addr === "h80".U ) -> cReg.statDownRecErrorCnt(7,0),
        (addr === "h81".U ) -> cReg.statDownRecErrorCnt(15,8),
        (addr === "h82".U ) -> cReg.statDownRecHeaderErrorCnt(7,0),
        (addr === "h83".U ) -> cReg.statDownRecHeaderErrorCnt(15,8),
        (addr === "h84".U ) -> cReg.statDownRecSubHeaderErrorCnt(7,0),
        (addr === "h85".U ) -> cReg.statDownRecSubHeaderErrorCnt(15,8),
        (addr === "h86".U ) -> cReg.statDownRecPayloadErrorCnt(7,0),
        (addr === "h87".U ) -> cReg.statDownRecPayloadErrorCnt(15,8),
        (addr === "h88".U ) -> cReg.statDownRecSubTailErrorCnt(7,0),
        (addr === "h89".U ) -> cReg.statDownRecSubTailErrorCnt(15,8),
        (addr === "h8a".U ) -> cReg.statDownRecCRCErrorCnt(7,0),
        (addr === "h8b".U ) -> cReg.statDownRecCRCErrorCnt(15,8),
        (addr === "h8c".U ) -> cReg.statDownRecFinishCnt(7,0),
        (addr === "h8d".U ) -> cReg.statDownRecFinishCnt(15,8),
        (addr === "h8e".U ) -> cReg.statDownRecFinishCnt(23,16),
        (addr === "h8f".U ) -> cReg.statDownRecFinishCnt(31,24),
        (addr === "h90".U ) -> cReg.statDownRecByteCnt(7,0),
        (addr === "h91".U ) -> cReg.statDownRecByteCnt(15,8),
        (addr === "h92".U ) -> cReg.statDownRecByteCnt(23,16),
        (addr === "h93".U ) -> cReg.statDownRecByteCnt(31,24),
        (addr === "h94".U ) -> cReg.statDownRecByteCnt(39,32),
        (addr === "h95".U ) -> cReg.statDownRecByteCnt(47,40),
        (addr === "h96".U ) -> cReg.statDownRecByteCnt(55,48),
        (addr === "h97".U ) -> cReg.statDownRecByteCnt(63,56),


        (addr === "ha0".U ) -> cReg.statUpRecErrorCnt(7,0),
        (addr === "ha1".U ) -> cReg.statUpRecErrorCnt(15,8),
        (addr === "ha2".U ) -> cReg.statUpRecHeaderErrorCnt(7,0),
        (addr === "ha3".U ) -> cReg.statUpRecHeaderErrorCnt(15,8),
        (addr === "ha4".U ) -> cReg.statUpRecSubHeaderErrorCnt(7,0),
        (addr === "ha5".U ) -> cReg.statUpRecSubHeaderErrorCnt(15,8),
        (addr === "ha6".U ) -> cReg.statUpRecPayloadErrorCnt(7,0),
        (addr === "ha7".U ) -> cReg.statUpRecPayloadErrorCnt(15,8),
        (addr === "ha8".U ) -> cReg.statUpRecSubTailErrorCnt(7,0),
        (addr === "ha9".U ) -> cReg.statUpRecSubTailErrorCnt(15,8),
        (addr === "haa".U ) -> cReg.statUpRecCRCErrorCnt(7,0),
        (addr === "hab".U ) -> cReg.statUpRecCRCErrorCnt(15,8),
        (addr === "hac".U ) -> cReg.statUpRecFinishCnt(7,0),
        (addr === "had".U ) -> cReg.statUpRecFinishCnt(15,8),
        (addr === "hae".U ) -> cReg.statUpRecFinishCnt(23,16),
        (addr === "haf".U ) -> cReg.statUpRecFinishCnt(31,24),
        (addr === "hb0".U ) -> cReg.statUpRecByteCnt(7,0),
        (addr === "hb1".U ) -> cReg.statUpRecByteCnt(15,8),
        (addr === "hb2".U ) -> cReg.statUpRecByteCnt(23,16),
        (addr === "hb3".U ) -> cReg.statUpRecByteCnt(31,24),
        (addr === "hb4".U ) -> cReg.statUpRecByteCnt(39,32),
        (addr === "hb5".U ) -> cReg.statUpRecByteCnt(47,40),
        (addr === "hb6".U ) -> cReg.statUpRecByteCnt(55,48),
        (addr === "hb7".U ) -> cReg.statUpRecByteCnt(63,56),




        (addr === "hc0".U ) -> Cat( sReg.isDevOnRightModify, sReg.isDevOnRight, 0.U(3.W) ),
        (addr === "hc2".U ) -> sReg.indexOfRightDev(7,0),
        (addr === "hc3".U ) -> sReg.indexOfRightDev(13,8),
        // (addr === "hc4".U ) -> sReg.indexOfLeftDev(7,0),
        // (addr === "hc5".U ) -> sReg.indexOfLeftDev(13,8),
      ) ++

      Seq(
        //本地时钟
        (addr === "h100".U )  -> cReg.timeStamp(7,0),
        (addr === "h101".U )  -> cReg.timeStamp(15,8),
        (addr === "h102".U )  -> cReg.timeStamp(23,16),
        (addr === "h103".U )  -> cReg.timeStamp(31,24),
        (addr === "h104".U )  -> cReg.timeStamp(39,32),
        (addr === "h105".U )  -> cReg.timeStamp(47,40),
        (addr === "h106".U )  -> cReg.timeStamp(55,48),
        (addr === "h107".U )  -> cReg.timeStamp(63,56),

        //参考主站时钟
        (addr === "h108".U & isSlvMode)  -> sReg.deltaFinal(7,0),
        (addr === "h109".U & isSlvMode)  -> sReg.deltaFinal(15,8),
        (addr === "h10a".U & isSlvMode)  -> sReg.deltaFinal(23,16),
        (addr === "h10b".U & isSlvMode)  -> sReg.deltaFinal(31,24),
        // (addr === "h10c".U & isSlvMode)  -> sReg.deltaFinal(39,32),
        // (addr === "h10d".U & isSlvMode)  -> sReg.deltaFinal(47,40),
        // (addr === "h10e".U & isSlvMode)  -> sReg.deltaFinal(55,48),
        // (addr === "h10f".U & isSlvMode)  -> sReg.deltaFinal(63,56),

        //主站发送接收时间差
        (addr === "h110".U )  -> cReg.mstDeltaTime(7,0),  
        (addr === "h111".U )  -> cReg.mstDeltaTime(15,8), 
        (addr === "h112".U )  -> cReg.mstDeltaTime(23,16),
        (addr === "h113".U )  -> cReg.mstDeltaTime(31,24),

        //从站发送接收时间差
        (addr === "h114".U & isSlvMode)  -> sReg.slvDeltaTime(7,0),  
        (addr === "h115".U & isSlvMode)  -> sReg.slvDeltaTime(15,8), 
        (addr === "h116".U & isSlvMode)  -> sReg.slvDeltaTime(23,16),
        (addr === "h117".U & isSlvMode)  -> sReg.slvDeltaTime(31,24),

        //校准后的时钟
        (addr === "h118".U )  -> cReg.recoTimeStamp(7,0),
        (addr === "h119".U )  -> cReg.recoTimeStamp(15,8),
        (addr === "h11a".U )  -> cReg.recoTimeStamp(23,16),
        (addr === "h11b".U )  -> cReg.recoTimeStamp(31,24),
        (addr === "h11c".U )  -> cReg.recoTimeStamp(39,32),
        (addr === "h11d".U )  -> cReg.recoTimeStamp(47,40),
        (addr === "h11e".U )  -> cReg.recoTimeStamp(55,48),
        (addr === "h11f".U )  -> cReg.recoTimeStamp(63,56),

        (addr === "h120".U )  -> cReg.syncCfg,

        (addr === "h122".U )  -> cReg.syncWidth(0)(7,0),
        (addr === "h123".U )  -> cReg.syncWidth(0)(15,8),

        (addr === "h124".U )  -> cReg.syncWidth(1)(7,0),
        (addr === "h125".U )  -> cReg.syncWidth(1)(15,8),

        (addr === "h126".U )  -> cReg.syncWidth(2)(7,0),
        (addr === "h127".U )  -> cReg.syncWidth(2)(15,8),

        (addr === "h128".U )  -> cReg.syncWidth(3)(7,0),
        (addr === "h129".U )  -> cReg.syncWidth(3)(15,8),

        (addr === "h130".U )  -> cReg.syncPoint(7,0),
        (addr === "h131".U )  -> cReg.syncPoint(15,8),
        (addr === "h132".U )  -> cReg.syncPoint(23,16),
        (addr === "h133".U )  -> cReg.syncPoint(31,24),
        (addr === "h134".U )  -> cReg.syncPoint(39,32),
        (addr === "h135".U )  -> cReg.syncPoint(47,40),
        (addr === "h136".U )  -> cReg.syncPoint(55,48),
        (addr === "h137".U )  -> cReg.syncPoint(63,56),

        (addr === "h138".U )  -> cReg.syncPeroid(7,0),
        (addr === "h139".U )  -> cReg.syncPeroid(15,8),
        (addr === "h13a".U )  -> cReg.syncPeroid(23,16),
        (addr === "h13b".U )  -> cReg.syncPeroid(31,24),

        (addr === "h13c".U )  -> cReg.syncOffset(1)(7,0),
        (addr === "h13d".U )  -> cReg.syncOffset(1)(15,8),
        (addr === "h13e".U )  -> cReg.syncOffset(1)(23,16),
        (addr === "h13f".U )  -> cReg.syncOffset(1)(31,24),

        (addr === "h140".U )  -> cReg.syncOffset(2)(7,0),
        (addr === "h141".U )  -> cReg.syncOffset(2)(15,8),
        (addr === "h142".U )  -> cReg.syncOffset(2)(23,16),
        (addr === "h143".U )  -> cReg.syncOffset(2)(31,24),

        (addr === "h144".U )  -> cReg.syncOffset(3)(7,0),
        (addr === "h145".U )  -> cReg.syncOffset(3)(15,8),
        (addr === "h146".U )  -> cReg.syncOffset(3)(23,16),
        (addr === "h147".U )  -> cReg.syncOffset(3)(31,24),

        (addr === "h148".U )  -> cReg.localPoint(7,0),
        (addr === "h149".U )  -> cReg.localPoint(15,8),
        (addr === "h14a".U )  -> cReg.localPoint(23,16),
        (addr === "h14b".U )  -> cReg.localPoint(31,24),
        (addr === "h14c".U )  -> cReg.localPoint(39,32),
        (addr === "h14d".U )  -> cReg.localPoint(47,40),
        (addr === "h14e".U )  -> cReg.localPoint(55,48),
        (addr === "h14f".U )  -> cReg.localPoint(63,56),

        (addr === "h150".U )  -> cReg.localPeroid(7,0),
        (addr === "h151".U )  -> cReg.localPeroid(15,8),
        (addr === "h152".U )  -> cReg.localPeroid(23,16),
        (addr === "h153".U )  -> cReg.localPeroid(31,24),

      ) ++
      ( 0 until 128 ).map{ i =>
        ( addr === ("h180".U(16.W) + i.U )   ) -> cReg.custom(i)
      } ++
      ( 0 until 16 ).map{ i => Seq(
        ( ( addr === ( "h200".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).lAddr( 7, 0),
        ( ( addr === ( "h201".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).lAddr(15, 8),
        ( ( addr === ( "h202".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).lAddr(23,16),
        ( ( addr === ( "h203".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).lAddr(29,24),

        ( ( addr === ( "h204".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).pAddr( 7, 0),
        ( ( addr === ( "h205".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).pAddr(15, 8),

        ( ( addr === ( "h206".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).length( 7, 0),
        ( ( addr === ( "h207".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).length(15, 8),

        ( ( addr === ( "h208".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).op,
        ( ( addr === ( "h209".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).isEnable,
      )}.reduce(_++_) ++
      ( 0 until 8 ).map{ i =>
        ( addr === ("h301".U(16.W) + (i*4).U) )  -> cReg.smUsedDepth(i)
      } ++
      ( 0 until 8 ).map{ i =>
        ( addr === ("h302".U(16.W) + (i*4).U) )  -> cReg.smTrigLen(i)(7,0)
      } ++
      ( 0 until 8 ).map{ i =>
        ( addr === ("h303".U(16.W) + (i*4).U) )  -> cReg.smTrigLen(i)(10,8)
      } ++

      ( 0 until 4 ).map{ i =>
        ( addr === ("h400".U(16.W) + i.U) )  -> cReg.wdtStatus( 8*i+7, 8*i+0 )
      } ++
      ( 0 until 4 ).map{ i =>
        ( addr === ("h404".U(16.W) + i.U) )  -> cReg.wdtEnable( 8*i+7, 8*i+0 )
      } ++
      (for( i <- 0 until 17; j <- 0 until 4 ) yield {
        ( addr === ("h408".U(16.W) + (4*i+j).U) )  -> cReg.wdtTarCnt(i)( 8*j+7, 8*j+0 )
      }) ++
      Seq(
        (addr === "h500".U )  -> cReg.event.latchCtl(0),
        (addr === "h502".U )  -> cReg.event.latchCtl(1),
        (addr === "h504".U )  -> cReg.event.latchStatus(0),
        (addr === "h506".U )  -> cReg.event.latchStatus(1),
      ) ++
      ( 0 until 8 ).map{ i =>
        ( addr === ("h508".U(16.W) + i.U) )  -> cReg.event.posedgeTimeStampLatch(0)( 8*i+7, 8*i+0 )
      } ++
      ( 0 until 8 ).map{ i =>
        ( addr === ("h510".U(16.W) + i.U) )  -> cReg.event.negedgeTimeStampLatch(0)( 8*i+7, 8*i+0 )
      } ++
      ( 0 until 8 ).map{ i =>
        ( addr === ("h518".U(16.W) + i.U) )  -> cReg.event.posedgeTimeStampLatch(1)( 8*i+7, 8*i+0 )
      } ++
      ( 0 until 8 ).map{ i =>
        ( addr === ("h520".U(16.W) + i.U) )  -> cReg.event.negedgeTimeStampLatch(1)( 8*i+7, 8*i+0 )
      } ++
      ( 0 until 8 ).map{ i =>
        ( addr === ("h528".U(16.W) + i.U) )  -> cReg.event.mcuSMTimeStampEnq( 8*i+7, 8*i+0 )
      } ++
      ( 0 until 8 ).map{ i =>
        ( addr === ("h530".U(16.W) + i.U) )  -> cReg.event.mcuSMTimeStampDeq( 8*i+7, 8*i+0 )
      } ++
      ( 0 until 8 ).map{ i =>
        ( addr === ("h538".U(16.W) + i.U) )  -> cReg.event.lvdsSMTimeStampEnq( 8*i+7, 8*i+0 )
      } ++
      ( 0 until 8 ).map{ i =>
        ( addr === ("h540".U(16.W) + i.U) )  -> cReg.event.lvdsSMTimeStampDeq( 8*i+7, 8*i+0 )
      } ++
      Seq()

    )


  }



  //spi信号
  val addrr = Wire(UInt(16.W))
  val addrw = Wire(UInt(16.W))
  val dataw   = Wire( UInt(8.W) )
  val datar   = Wire( UInt(8.W) )  
  val isEnW = Wire(Bool())
  val isEnR = Wire(Bool())


}

trait InterfaceMCUop{ this: InterfaceBase =>







  isEnW := Mux1H(Seq(
    ( cReg.spiSel === 0.U ) -> iQSpi.io.isEnW,
    ( cReg.spiSel === 1.U ) ->  oSpi.io.isEnW,
    ( cReg.spiSel === 2.U ) -> oQSpi.io.isEnW,
  ))
    
  addrr := Mux1H(Seq(
    ( cReg.spiSel === 0.U ) -> iQSpi.io.addrr,
    ( cReg.spiSel === 1.U ) ->  oSpi.io.addrr,
    ( cReg.spiSel === 2.U ) -> oQSpi.io.addrr,
  ))

  addrw := Mux1H(Seq(
    ( cReg.spiSel === 0.U ) -> iQSpi.io.addrw,
    ( cReg.spiSel === 1.U ) ->  oSpi.io.addrw,
    ( cReg.spiSel === 2.U ) -> oQSpi.io.addrw,
  ))

  dataw := Mux1H(Seq(
    ( cReg.spiSel === 0.U ) -> iQSpi.io.dataw,
    ( cReg.spiSel === 1.U ) ->  oSpi.io.dataw,
    ( cReg.spiSel === 2.U ) -> oQSpi.io.dataw,
  ))

  isEnR := Mux1H(Seq(
    ( cReg.spiSel === 0.U ) -> iQSpi.io.isEnR,
    ( cReg.spiSel === 1.U ) ->  oSpi.io.isEnR,
    ( cReg.spiSel === 2.U ) -> oQSpi.io.isEnR,
  ))

  datar := MuxCase( 0.U, Array(
      ((addrr & "hF800".U) === "h0000".U) -> RegEnable( AcquireReg(addr = addrr), isEnR ),
      ((addrr & "hF800".U) === "h0800".U) -> io.sram_r(0).datar,
      ((addrr & "hF800".U) === "h1000".U) -> 0.U,
      ((addrr & "hF800".U) === "h1800".U) -> io.sram_r(1).datar,
      ((addrr & "hF800".U) === "h2000".U) -> 0.U,
      ((addrr & "hF800".U) === "h2800".U) -> io.sram_r(2).datar,
      ((addrr & "hF800".U) === "h3000".U) -> 0.U,
      ((addrr & "hF800".U) === "h3800".U) -> io.sram_r(3).datar,
      ((addrr & "hF800".U) === "h4000".U) -> 0.U,
    ))

  iQSpi.io.datar := Mux(cReg.spiSel === 0.U, datar, 0.U)
   oSpi.io.datar := Mux(cReg.spiSel === 1.U, datar, 0.U)
  oQSpi.io.datar := Mux(cReg.spiSel === 2.U, datar, 0.U)

  // when( isEnW ){
  //   printf(s"SPI/QSPI Write 0x%x, @0x%x\n", dataw, addrw)
  // }
  // when( isEnR ){
  //   printf(s"SPI/QSPI Readout 0x%x, @0x%x\n", datar, addrr)
  // }



  cReg.mstOrSlv  := RegEnable( dataw(1,0), 0.U, isEnW & addrw === "h0".U & cReg.mstOrSlv === 0.U )
  cReg.hwVersion := RegEnable( dataw     , "hF0".U, isEnW & addrw === "h1".U & cReg.mstOrSlv === 0.U )

  cReg.hwSerial := 
    Cat(
      (0 until 6).map{ i =>
      RegEnable( dataw, "haa".U, isEnW & addrw === ("h2".U(16.W) + i.U) & cReg.mstOrSlv === 0.U )
      }.reverse
    )
  
  cReg.busRate := RegEnable( dataw, "h55".U, isEnW & addrw === "h8".U & cReg.mstOrSlv === 0.U )
  cReg.spiSel  := RegEnable( dataw(1,0), 0.U, isEnW & addrw === "h9".U & cReg.mstOrSlv === 0.U )


  mReg.txSM     := RegEnable( dataw(2,1), 0.U, isEnW & addrw === "h20".U )
  mReg.rxSM     := RegEnable( dataw(4,3), 0.U, isEnW & addrw === "h20".U )
  // mReg.txLength := Cat( RegEnable( dataw, 0.U, isEnW & addrw === "h22".U ), RegEnable( dataw, 0.U, isEnW & addrw === "h21".U ) )

  ( 0 until 128 ).map{ i =>
    cReg.custom(i) := RegEnable( dataw, 0.U, isEnW & (addrw === ("h180".U(16.W) + i.U)) )
  }

  val rplTimeStampTx = RegInit(0.U(16.W))

  mReg.rplTimeStampTx := rplTimeStampTx

  when( io.intMstTrig(0) ){
    rplTimeStampTx := rplTimeStampTx & "h3FFF".U(16.W)
  } .elsewhen( isEnW & addrw === "h25".U ){
    rplTimeStampTx := Cat( dataw, rplTimeStampTx(7,0) )
  } .elsewhen( isEnW & addrw === "h24".U ){
    rplTimeStampTx := Cat(rplTimeStampTx(15,8), dataw )
  }







}

trait InterfaceCheckSM{ this: InterfaceBase =>
  val isEnW: Bool
  val addrw: UInt
  val dataw: UInt
  val isEnR: Bool


  val smTrigLen_H = for( i <- 0 until 8 ) yield { RegInit(0.U(8.W)) }
  val smTrigLen_L = for( i <- 0 until 8 ) yield { RegInit(0.U(8.W)) }


  for( i <- 0 until 8 ){

    io.isSMReset(i) := isEnW & (addrw === ("h300".U(16.W) + (i*4).U))

    cReg.smUsedDepth(i) := io.smUsedDepth(i)
    cReg.smTrigLen(i) := Cat( smTrigLen_H(i), smTrigLen_L(i) )

    when( isEnW & addrw === ("h303".U(16.W) + (i*4).U) ){
      smTrigLen_H(i) := dataw
    } .elsewhen( io.lvds.isEnW & io.lvds.addrw === ("h303".U(16.W) + (i*4).U)){
      smTrigLen_H(i) := io.lvds.dataw
    }

    when( isEnW & addrw === ("h302".U(16.W) + (i*4).U) ){
      smTrigLen_L(i) := dataw
    } .elsewhen( io.lvds.isEnW & io.lvds.addrw === ("h302".U(16.W) + (i*4).U)){
      smTrigLen_L(i) := io.lvds.dataw
    }

  }


  io.sram_r(0).addrr := addrr
  io.sram_r(1).addrr := addrr
  io.sram_r(2).addrr := addrr
  io.sram_r(3).addrr := addrr

  io.sram_r(0).enr   := isEnR & (( addrr & "hF800".U ) === "h0800".U)
  io.sram_r(1).enr   := isEnR & (( addrr & "hF800".U ) === "h1800".U)
  io.sram_r(2).enr   := isEnR & (( addrr & "hF800".U ) === "h2800".U)
  io.sram_r(3).enr   := isEnR & (( addrr & "hF800".U ) === "h3800".U)

  io.sram_w(0).addrw := addrw
  io.sram_w(1).addrw := addrw
  io.sram_w(2).addrw := addrw
  io.sram_w(3).addrw := addrw

  io.sram_w(0).dataw := dataw
  io.sram_w(1).dataw := dataw
  io.sram_w(2).dataw := dataw
  io.sram_w(3).dataw := dataw

  io.sram_w(0).enw   := isEnW & (( addrw & "hF800".U ) === "h1000".U)
  io.sram_w(1).enw   := isEnW & (( addrw & "hF800".U ) === "h2000".U)
  io.sram_w(2).enw   := isEnW & (( addrw & "hF800".U ) === "h3000".U)
  io.sram_w(3).enw   := isEnW & (( addrw & "hF800".U ) === "h4000".U)

  io.dSMdeq(0) := isEnR & (( addrr & "hF800".U ) === "h0800".U) & (addrr(10,0) === cReg.smTrigLen(0) - 1.U + 1.U)
  io.dSMdeq(1) := isEnR & (( addrr & "hF800".U ) === "h1800".U) & (addrr(10,0) === cReg.smTrigLen(2) - 1.U + 1.U)
  io.dSMdeq(2) := isEnR & (( addrr & "hF800".U ) === "h2800".U) & (addrr(10,0) === cReg.smTrigLen(4) - 1.U + 1.U)
  io.dSMdeq(3) := isEnR & (( addrr & "hF800".U ) === "h3800".U) & (addrr(10,0) === cReg.smTrigLen(6) - 1.U + 1.U)

  io.uSMenq(0) := isEnW & (( addrw & "hF800".U ) === "h1000".U) & (addrw(10,0) === cReg.smTrigLen(1) - 1.U)
  io.uSMenq(1) := isEnW & (( addrw & "hF800".U ) === "h2000".U) & (addrw(10,0) === cReg.smTrigLen(3) - 1.U)
  io.uSMenq(2) := isEnW & (( addrw & "hF800".U ) === "h3000".U) & (addrw(10,0) === cReg.smTrigLen(5) - 1.U)
  io.uSMenq(3) := isEnW & (( addrw & "hF800".U ) === "h4000".U) & (addrw(10,0) === cReg.smTrigLen(7) - 1.U)
}

trait InterfaceLVDSop{ this: InterfaceBase =>
  
  io.lvds.datar := RegEnable(AcquireReg(addr = io.lvds.addrr), io.lvds.isEnR)


  ( 0 until 16 ).map{ i =>
    sReg.ebmmu(i).lAddr := Cat(
      RegEnable( io.lvds.dataw(5,0), 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h203".U(16.W) + (10*i).U )) ),
      RegEnable( io.lvds.dataw,      0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h202".U(16.W) + (10*i).U )) ),
      RegEnable( io.lvds.dataw,      0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h201".U(16.W) + (10*i).U )) ),
      RegEnable( io.lvds.dataw,      0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h200".U(16.W) + (10*i).U )) ),
    )

    sReg.ebmmu(i).pAddr := Cat(
      RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h205".U(16.W) + (10*i).U )) ),
      RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h204".U(16.W) + (10*i).U )) ),
    )

    sReg.ebmmu(i).length := Cat(
      RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h207".U(16.W) + (10*i).U )) ),
      RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h206".U(16.W) + (10*i).U )) ),
    )

    sReg.ebmmu(i).op :=
      RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h208".U(16.W) + (10*i).U )) )

    sReg.ebmmu(i).isEnable :=
      RegEnable( io.lvds.dataw.extract(0), false.B, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h209".U(16.W) + (10*i).U )) )
  }

}

trait InterfaceSync{ this: InterfaceBase =>

  val syncCfg = RegInit(0.U(8.W)); cReg.syncCfg := syncCfg

  val syncWidth = for( i <- 0 until 4 ) yield { RegInit(0.U(16.W)) }
  for( i <- 0 until 4 ) {
    cReg.syncWidth(i) := syncWidth(i)
  }

  val syncPoint   = RegInit(0.U(64.W)); cReg.syncPoint := syncPoint
  val syncPeroid  = RegInit(0.U(32.W)); cReg.syncPeroid := syncPeroid
  val localPoint   = RegInit(0.U(64.W)); cReg.localPoint  := localPoint
  val localPeroid  = RegInit(0.U(32.W)); cReg.localPeroid := localPeroid

  val syncOffset = for( i <- 0 until 4 ) yield { RegInit(0.U(32.W)) } //空开0
  for( i <- 0 until 4 ) {
    cReg.syncOffset(i) := syncOffset(i)
  }

  when( isEnW ){
    when( addrw === "h120".U ){
      syncCfg := dataw
    }

    for( i <- 0 until 4 ){
      when( io.lvds.addrw === ("h122".U(16.W) + (2*i).U)){
        syncWidth(i) := Cat( syncWidth(i)(15,8), io.lvds.dataw ) 
      } .elsewhen( io.lvds.addrw === ("h123".U(16.W) + (2*i).U) ){
        syncWidth(i) := Cat( io.lvds.dataw, syncWidth(i)(7,0) ) 
      }
    }

    when( addrw === "h130".U ){
      syncPoint := Cat( syncPoint(63,8), dataw ) 
    } .elsewhen( addrw === "h131".U ){
      syncPoint := Cat( syncPoint(63,16), dataw, syncPoint(7,0) ) 
    } .elsewhen( addrw === "h132".U ){
      syncPoint := Cat( syncPoint(63,24), dataw, syncPoint(15,0) ) 
    } .elsewhen( addrw === "h133".U ){
      syncPoint := Cat( syncPoint(63,32), dataw, syncPoint(23,0) ) 
    } .elsewhen( addrw === "h134".U ){
      syncPoint := Cat( syncPoint(63,40), dataw, syncPoint(31,0) ) 
    } .elsewhen( addrw === "h135".U ){
      syncPoint := Cat( syncPoint(63,48), dataw, syncPoint(39,0) ) 
    } .elsewhen( addrw === "h136".U ){
      syncPoint := Cat( syncPoint(63,56), dataw, syncPoint(47,0) ) 
    } .elsewhen( addrw === "h137".U ){
      syncPoint := Cat( dataw, syncPoint(55,0) ) 
    }

    .elsewhen( addrw === "h138".U ){
      syncPeroid := Cat( syncPeroid(31,8), dataw ) 
    } .elsewhen( addrw === "h139".U ){
      syncPeroid := Cat( syncPeroid(31,16), dataw, syncPeroid(7,0) ) 
    } .elsewhen( addrw === "h13a".U ){
      syncPeroid := Cat( syncPeroid(31,24), dataw, syncPeroid(15,0) ) 
    } .elsewhen( addrw === "h13b".U ){
      syncPeroid := Cat( dataw, syncPeroid(23,0) ) 
    }

    .elsewhen( addrw === "h148".U ){
      localPoint := Cat( localPoint(63,8), dataw ) 
    } .elsewhen( addrw === "h149".U ){
      localPoint := Cat( localPoint(63,16), dataw, localPoint(7,0) ) 
    } .elsewhen( addrw === "h14a".U ){
      localPoint := Cat( localPoint(63,24), dataw, localPoint(15,0) ) 
    } .elsewhen( addrw === "h14b".U ){
      localPoint := Cat( localPoint(63,32), dataw, localPoint(23,0) ) 
    } .elsewhen( addrw === "h14c".U ){
      localPoint := Cat( localPoint(63,40), dataw, localPoint(31,0) ) 
    } .elsewhen( addrw === "h14d".U ){
      localPoint := Cat( localPoint(63,48), dataw, localPoint(39,0) ) 
    } .elsewhen( addrw === "h14e".U ){
      localPoint := Cat( localPoint(63,56), dataw, localPoint(47,0) ) 
    } .elsewhen( addrw === "h14f".U ){
      localPoint := Cat( dataw, localPoint(55,0) ) 
    }

    .elsewhen( addrw === "h150".U ){
      localPeroid := Cat( localPeroid(31,8), dataw ) 
    } .elsewhen( addrw === "h151".U ){
      localPeroid := Cat( localPeroid(31,16), dataw, localPeroid(7,0) ) 
    } .elsewhen( addrw === "h152".U ){
      localPeroid := Cat( localPeroid(31,24), dataw, localPeroid(15,0) ) 
    } .elsewhen( addrw === "h153".U ){
      localPeroid := Cat( dataw, localPeroid(23,0) ) 
    }



    for( i <- 1 until 4 ){
      when( addrw === ("h13c".U(16.W) + (4*(i-1)).U) ){
        syncOffset(i) := Cat( syncOffset(i)(31,8), dataw ) 
      } .elsewhen( addrw === ("h13d".U(16.W) + (4*(i-1)).U) ){
        syncOffset(i) := Cat( syncOffset(i)(31,16), dataw, syncOffset(i)(7,0) ) 
      } .elsewhen( addrw === ("h13e".U(16.W) + (4*(i-1)).U) ){
        syncOffset(i) := Cat( syncOffset(i)(31,24), dataw, syncOffset(i)(15,0) ) 
      } .elsewhen( addrw === ("h13f".U(16.W) + (4*(i-1)).U) ){
        syncOffset(i) := Cat( dataw, syncOffset(i)(23,0) ) 
      }      
    }
  }



  when( io.lvds.isEnW ){

    when( io.lvds.addrw === "h120".U ){
      syncCfg := io.lvds.dataw
    }

    for( i <- 0 until 4 ){
      when( io.lvds.addrw === ("h122".U(16.W) + (2*i).U)){
        syncWidth(i) := Cat( syncWidth(i)(15,8), io.lvds.dataw ) 
      } .elsewhen( io.lvds.addrw === ("h123".U(16.W) + (2*i).U) ){
        syncWidth(i) := Cat( io.lvds.dataw, syncWidth(i)(7,0) ) 
      }
    }

    .elsewhen( io.lvds.addrw === "h130".U ){
      syncPoint := Cat( syncPoint(63,8), io.lvds.dataw ) 
    } .elsewhen( io.lvds.addrw === "h131".U ){
      syncPoint := Cat( syncPoint(63,16), io.lvds.dataw, syncPoint(7,0) ) 
    } .elsewhen( io.lvds.addrw === "h132".U ){
      syncPoint := Cat( syncPoint(63,24), io.lvds.dataw, syncPoint(15,0) ) 
    } .elsewhen( io.lvds.addrw === "h133".U ){
      syncPoint := Cat( syncPoint(63,32), io.lvds.dataw, syncPoint(23,0) ) 
    } .elsewhen( io.lvds.addrw === "h134".U ){
      syncPoint := Cat( syncPoint(63,40), io.lvds.dataw, syncPoint(31,0) ) 
    } .elsewhen( io.lvds.addrw === "h135".U ){
      syncPoint := Cat( syncPoint(63,48), io.lvds.dataw, syncPoint(39,0) ) 
    } .elsewhen( io.lvds.addrw === "h136".U ){
      syncPoint := Cat( syncPoint(63,56), io.lvds.dataw, syncPoint(47,0) ) 
    } .elsewhen( io.lvds.addrw === "h137".U ){
      syncPoint := Cat( io.lvds.dataw, syncPoint(55,0) ) 
    }

    .elsewhen( io.lvds.addrw === "h138".U ){
      syncPeroid := Cat( syncPeroid(31,8), io.lvds.dataw ) 
    } .elsewhen( io.lvds.addrw === "h139".U ){
      syncPeroid := Cat( syncPeroid(31,16), io.lvds.dataw, syncPeroid(7,0) ) 
    } .elsewhen( io.lvds.addrw === "h13a".U ){
      syncPeroid := Cat( syncPeroid(31,24), io.lvds.dataw, syncPeroid(15,0) ) 
    } .elsewhen( io.lvds.addrw === "h13b".U ){
      syncPeroid := Cat( io.lvds.dataw, syncPeroid(23,0) ) 
    }

    .elsewhen( io.lvds.addrw === "h148".U ){
      localPoint := Cat( localPoint(63,8), io.lvds.dataw ) 
    } .elsewhen( io.lvds.addrw === "h149".U ){
      localPoint := Cat( localPoint(63,16), io.lvds.dataw, localPoint(7,0) ) 
    } .elsewhen( io.lvds.addrw === "h14a".U ){
      localPoint := Cat( localPoint(63,24), io.lvds.dataw, localPoint(15,0) ) 
    } .elsewhen( io.lvds.addrw === "h14b".U ){
      localPoint := Cat( localPoint(63,32), io.lvds.dataw, localPoint(23,0) ) 
    } .elsewhen( io.lvds.addrw === "h14c".U ){
      localPoint := Cat( localPoint(63,40), io.lvds.dataw, localPoint(31,0) ) 
    } .elsewhen( io.lvds.addrw === "h14d".U ){
      localPoint := Cat( localPoint(63,48), io.lvds.dataw, localPoint(39,0) ) 
    } .elsewhen( io.lvds.addrw === "h14e".U ){
      localPoint := Cat( localPoint(63,56), io.lvds.dataw, localPoint(47,0) ) 
    } .elsewhen( io.lvds.addrw === "h14f".U ){
      localPoint := Cat( io.lvds.dataw, localPoint(55,0) ) 
    }

    .elsewhen( io.lvds.addrw === "h150".U ){
      localPeroid := Cat( localPeroid(31,8), io.lvds.dataw ) 
    } .elsewhen( io.lvds.addrw === "h151".U ){
      localPeroid := Cat( localPeroid(31,16), io.lvds.dataw, localPeroid(7,0) ) 
    } .elsewhen( io.lvds.addrw === "h152".U ){
      localPeroid := Cat( localPeroid(31,24), io.lvds.dataw, localPeroid(15,0) ) 
    } .elsewhen( io.lvds.addrw === "h153".U ){
      localPeroid := Cat( io.lvds.dataw, localPeroid(23,0) ) 
    }


    for( i <- 1 until 4 ){
      when( io.lvds.addrw === ("h13c".U(16.W) + (4*(i-1)).U) ){
        syncOffset(i) := Cat( syncOffset(i)(31,8), io.lvds.dataw ) 
      } .elsewhen( io.lvds.addrw === ("h13d".U(16.W) + (4*(i-1)).U) ){
        syncOffset(i) := Cat( syncOffset(i)(31,16), io.lvds.dataw, syncOffset(i)(7,0) ) 
      } .elsewhen( io.lvds.addrw === ("h13e".U(16.W) + (4*(i-1)).U) ){
        syncOffset(i) := Cat( syncOffset(i)(31,24), io.lvds.dataw, syncOffset(i)(15,0) ) 
      } .elsewhen( io.lvds.addrw === ("h13f".U(16.W) + (4*(i-1)).U) ){
        syncOffset(i) := Cat( io.lvds.dataw, syncOffset(i)(23,0) ) 
      }      
    }
  }

  cReg.timeStamp := RegNext( cReg.timeStamp + 1.U, 0.U )
  cReg.mstDeltaTime := io.mstDeltaTime


  sReg.deltaFinal := io.deltaFinal
  cReg.recoTimeStamp := 
    Mux(isMstMode, cReg.timeStamp,
      RegNext( cReg.timeStamp + Cat( Fill(32, sReg.deltaFinal.extract(31)), sReg.deltaFinal ) )
    )
  sReg.slvDeltaTime := io.slvDeltaTime
  
  val syncSign = for( i <- 0 until 4 ) yield { RegInit(false.B) }
  val syncOffsetCnt = for( i <- 0 until 4 ) yield { RegInit("hFFFFFFFF".U(32.W)) } //空开第0位
  val syncResetCnt = for( i <- 0 until 4 ) yield { RegInit(0.U(16.W)) } //空开第0位


  when( cReg.syncPoint === cReg.recoTimeStamp ){ //时间到达sync0时间点
    syncSign(0) := true.B
    syncPoint := syncPoint + cReg.syncPeroid
  } .elsewhen( ~cReg.syncCfg(4+0) & syncResetCnt(0) === cReg.syncWidth(0) ){
    syncSign(0) := false.B
  } .elsewhen( cReg.syncCfg(4+0) & isEnW & addrw === "h122".U ){
    syncSign(0) := false.B
  }

  for( i <- 1 until 4 ) {

    when( cReg.syncPoint === cReg.recoTimeStamp ){ //时间到达sync0时间点
      syncOffsetCnt(i) := 0.U
    } .elsewhen( syncOffsetCnt(i) < cReg.syncOffset(i) ){
      syncOffsetCnt(i) := syncOffsetCnt(i) + 1.U
    } .elsewhen( syncOffsetCnt(i) === cReg.syncOffset(i) ){
      syncOffsetCnt(i) := "hFFFFFFFF".U(32.W)
    }

    when( syncOffsetCnt(i) === cReg.syncOffset(i) ){
      syncSign(i) := true.B
    } .elsewhen( ~cReg.syncCfg(4+i) & syncResetCnt(i) === cReg.syncWidth(i) ){
      syncSign(i) := false.B
    } .elsewhen( cReg.syncCfg(4+i) & isEnW & addrw === ("h122".U(16.W) + (2*i).U) ){
      syncSign(i) := false.B
    }

  }

  for( i <- 0 until 4 ){
    when( ~cReg.syncCfg(4+i) ){
      when( syncSign(i) ){
        syncResetCnt(i) := syncResetCnt(i) + 1.U
      } .otherwise{
        syncResetCnt(i) := 0.U
      }
    }
  }

  io.sync(0) := cReg.syncCfg.extract(0) & syncSign(0)
  io.sync(1) := cReg.syncCfg.extract(1) & syncSign(1)
  io.sync(2) := cReg.syncCfg.extract(2) & syncSign(2)
  io.sync(3) := cReg.syncCfg.extract(3) & syncSign(3)


  val isLocalSyncInt = cReg.localPoint === cReg.recoTimeStamp

  when( isLocalSyncInt ){ //时间到达localSync时间点
    localPoint := cReg.localPoint + cReg.localPeroid
  }


}

trait InterfaceWdt{ this: InterfaceBase =>
  val wdtStatus = for( i <- 0 until 18 ) yield { RegInit(false.B) } //1+16+1
  cReg.wdtStatus := Cat( wdtStatus.reverse )

  for( i <- 0 until 8 ){
    when( isEnW & addrw === "h400".U & dataw.extract(i) ){
      wdtStatus(i) := false.B
    } .elsewhen(io.wdtTrigger(i) & cReg.wdtEnable.extract(i)){
      wdtStatus(i) := true.B
    }
    when( isEnW & addrw === "h401".U & dataw.extract(i) ){
      wdtStatus(8+i) := false.B
    } .elsewhen(io.wdtTrigger(8+i) & cReg.wdtEnable.extract(8+i)){
      wdtStatus(8+i) := true.B
    }
  }
  for( i <- 0 until 2 ){
    when( isEnW & addrw === "h402".U & dataw.extract(i) ){
      wdtStatus(16+i) := false.B
    } .elsewhen(io.wdtTrigger(16+i) & cReg.wdtEnable.extract(16+i)){
      wdtStatus(16+i) := true.B
    }
  }

  cReg.wdtEnable := 
    Cat(
      RegEnable( dataw(1,0), 0.U, isEnW & addrw === "h406".U ),
      RegEnable( dataw,            0.U, isEnW & addrw === "h405".U ),
      RegEnable( dataw,            0.U, isEnW & addrw === "h404".U ),
    )

  for( i <- 0 until 18 ){
    cReg.wdtTarCnt(i) :=
      Cat(
        RegEnable( dataw, 0.U, isEnW & addrw === ( "h40b".U (16.W) + (4*i).U ) ),
        RegEnable( dataw, 0.U, isEnW & addrw === ( "h40a".U (16.W) + (4*i).U ) ),
        RegEnable( dataw, 0.U, isEnW & addrw === ( "h409".U (16.W) + (4*i).U ) ),
        RegEnable( dataw, 0.U, isEnW & addrw === ( "h408".U (16.W) + (4*i).U ) ),
      )
  }
}

trait InterfaceSystem{ this: InterfaceBase =>
  io.isSoftReset :=
    cReg.softResetCode(0) === "h01".U &
    cReg.softResetCode(1) === "h00".U &
    cReg.softResetCode(2) === "h66".U &
    cReg.softResetCode(3) === "h79".U

  cReg.softResetCode(0) := RegEnable(dataw, 0.U, isEnW & addrw === "h40".U )
  cReg.softResetCode(1) := RegEnable(dataw, 0.U, isEnW & addrw === "h41".U )
  cReg.softResetCode(2) := RegEnable(dataw, 0.U, isEnW & addrw === "h42".U )
  cReg.softResetCode(3) := RegEnable(dataw, 0.U, isEnW & addrw === "h43".U )


  cReg.intEnable :=
    Cat(
      1.U(1.W), //复位中断，时钟为1 //31 上电复位
      1.U(1.W), //复位中断，时钟为1 //30 上行硬件错误
      1.U(1.W), //复位中断，时钟为1 //29 下行硬件错误
      RegEnable( dataw(4,0), 0.U, isEnW & addrw === "h73".U ),
      RegEnable( dataw, 0.U, isEnW & addrw === "h72".U ),
      RegEnable( dataw, 0.U, isEnW & addrw === "h71".U ),
      RegEnable( dataw, 0.U, isEnW & addrw === "h70".U ),
    )

  val intStatus = for( i <- 0 until 32 ) yield {
    if( i != 31 ) {RegInit(false.B)} else { RegInit(true.B) }
  }
  cReg.intStatus := Cat( intStatus.reverse )
  io.isPoReset := intStatus(31)

  cReg.intMode :=
    Cat(
      RegEnable( dataw, 0.U, isEnW & addrw === "h7d".U ),
      RegEnable( dataw, 0.U, isEnW & addrw === "h7c".U ),
    )

  val isLevelInt = cReg.intMode.extract(15) === false.B
  val isPulseInt = cReg.intMode.extract(15) === true.B
  val intPulseWidth = cReg.intMode(14,0)

  //主站发送完成
  when( io.intMstTrig(0) ){
    intStatus(0) := true.B
  }

  //主站接收完成
  when( io.intMstTrig(1) ){
    intStatus(1) := true.B
  }

  //主站发送周期到了
  val isLocalSyncInt: Bool
  when( isLocalSyncInt ){
    intStatus(2) := true.B
  }

  //外部latch中断
  val isLatchEvent = 
    (RegNext( cReg.event.latchStatus(0) ) =/= cReg.event.latchStatus(0)) |
    (RegNext( cReg.event.latchStatus(1) ) =/= cReg.event.latchStatus(1))

  when(isLatchEvent){
    intStatus(3) := true.B
  }

  //看门狗溢出
  val isWdtTrigAndEnable = (0 until 18).map{ i => (io.wdtTrigger(i) & cReg.wdtEnable(i))}.reduce(_|_)
  when( isWdtTrigAndEnable ){
    intStatus(4) := true.B
  }




  //从站SM请求
  for( i <- 0 until 8 ){
    when( io.intSlvTrig(i) ){
      intStatus(8+i) := true.B
    }
  }

  //传输完成请求 16,17,18,19
  for( i <- 0 until 4 ){
    when( io.intTransEnd(i) ){
      intStatus(16+i) := true.B
    }
  }

  //下行接收硬件错误
  when( io.intHWTrig(0) ){
    intStatus(29) := true.B
  }
  //上行接收硬件错误
  when( io.intHWTrig(1) ){
    intStatus(30) := true.B
  }


  //写清中断
  for( i <- 0 until 8 ){
    when( dataw.extract(i) & isEnW & addrw === "h78".U ){
      intStatus(i)    := false.B
    }
    when( dataw.extract(i) & isEnW & addrw === "h79".U ){
      intStatus(i+8)  := false.B
    }
    when( dataw.extract(i) & isEnW & addrw === "h7a".U ){
      intStatus(i+16) := false.B
    }
    when( dataw.extract(i) & isEnW & addrw === "h7b".U ){
      intStatus(i+24) := false.B
    }
  }

  io.intHWClr(0) := dataw.extract(5) & isEnW & addrw === "h7b".U 
  io.intHWClr(1) := dataw.extract(6) & isEnW & addrw === "h7b".U 

  val intPulse = RegInit(false.B)
  val intPulseResetCnt = RegInit(0.U(15.W))
  
  val trigIntPulse = 
    (io.intMstTrig(0) & cReg.intEnable(0)) | //主站发送完成
    (io.intMstTrig(1) & cReg.intEnable(1)) | //主站接收完成
    (isLocalSyncInt   & cReg.intEnable(2)) | //主站发送周期到了
    (isLatchEvent     & cReg.intEnable(3)) | //latch Event
    (~RegNext(isWdtTrigAndEnable, false.B) & isWdtTrigAndEnable & cReg.intEnable(4)) | //主站接收看门狗溢出
    (0 until 8).map{ i => io.intSlvTrig(i) & cReg.intEnable(8+i)}.reduce(_|_) | //从站SM请求
    (0 until 4).map{ i => io.intTransEnd(i) & cReg.intEnable(16+i)}.reduce(_|_) | //传输完成请求 16,17,18,19
    io.intHWTrig(0) | //下行接收硬件错误
    io.intHWTrig(1)   //上行接收硬件错误

  when( intPulseResetCnt === intPulseWidth ){
    intPulse := false.B
  } .elsewhen( trigIntPulse ){
    intPulse := true.B
  }

  when( trigIntPulse ){
    intPulseResetCnt := 0.U
  } .elsewhen( (intPulseResetCnt < intPulseWidth) & (intPulse === true.B) ){
    intPulseResetCnt := intPulseResetCnt + 1.U
  }

  io.interrupt := Mux( isLevelInt, (cReg.intStatus & cReg.intEnable).orR, intPulse)
  

}


trait InterfaceEvent{ this: InterfaceBase =>
  val isPosedgeOnce = for( i <- 0 until 2 ) yield RegEnable( dataw.extract(2), false.B, isEnW & ( addrw === ( "h500".U + (i*2).U ) ))
  val isNegedgeOnce = for( i <- 0 until 2 ) yield RegEnable( dataw.extract(3), false.B, isEnW & ( addrw === ( "h500".U + (i*2).U ) ))

  val isPosedgeLatch = for( i <- 0 until 2 ) yield RegInit(false.B)
  val isNegedgeLatch = for( i <- 0 until 2 ) yield RegInit(false.B)


  val posedgeTimeStampLatch = for( i <- 0 until 2 ) yield RegInit(0.U(64.W))
  val negedgeTimeStampLatch = for( i <- 0 until 2 ) yield RegInit(0.U(64.W))

  val mcuSMTimeStampEnq  = RegInit(0.U(64.W))
  val mcuSMTimeStampDeq  = RegInit(0.U(64.W))
  val lvdsSMTimeStampEnq = RegInit(0.U(64.W))
  val lvdsSMTimeStampDeq = RegInit(0.U(64.W))

  for( i <- 0 until 2 ){
    when( dataw.extract(0) & isEnW & ( addrw === ( "h500".U + (i*2).U ) ) ){
      isPosedgeLatch(i):= false.B
      posedgeTimeStampLatch(i) := 0.U
    } .elsewhen( ~RegNext(io.latchPin(i), false.B) & io.latchPin(i) ){
      when( isPosedgeOnce(i) ){
        isPosedgeLatch(i) := true.B
      }
      when(~isPosedgeLatch(i)){
        posedgeTimeStampLatch(i) := cReg.timeStamp
      }
    }

    when( dataw.extract(1) & isEnW & ( addrw === ( "h500".U + (i*2).U ) ) ){
      isNegedgeLatch(i) := false.B
      negedgeTimeStampLatch(i) := 0.U
    } .elsewhen( RegNext(io.latchPin(i), false.B) & ~io.latchPin(i) ){
      when( isNegedgeOnce(i) ){
        isNegedgeLatch(i) := true.B
      }
      when(~isNegedgeLatch(i)){
        negedgeTimeStampLatch(i) := cReg.timeStamp
      }
    }

    when( io.uSMenq.reduce(_|_) ){
      mcuSMTimeStampEnq := cReg.timeStamp
    }

    when( io.dSMdeq.reduce(_|_) ){
      mcuSMTimeStampDeq := cReg.timeStamp
    }

    when( io.lvdsSMEnq.reduce(_|_) ){
      lvdsSMTimeStampEnq := cReg.timeStamp
    }

    when( io.lvdsSMDeq.reduce(_|_) ){
      lvdsSMTimeStampDeq := cReg.timeStamp
    }

    cReg.event.latchCtl(i) := (isPosedgeOnce(i) << 2) | (isNegedgeOnce(i) << 3)

    cReg.event.latchStatus(i) := Cat( io.latchPin(i), isNegedgeLatch(i), isPosedgeLatch(i) )
    cReg.event.posedgeTimeStampLatch(i) := posedgeTimeStampLatch(i)
    cReg.event.negedgeTimeStampLatch(i) := negedgeTimeStampLatch(i)
  }

  cReg.event.mcuSMTimeStampEnq  := mcuSMTimeStampEnq
  cReg.event.mcuSMTimeStampDeq  := mcuSMTimeStampDeq
  cReg.event.lvdsSMTimeStampEnq := lvdsSMTimeStampEnq
  cReg.event.lvdsSMTimeStampDeq := lvdsSMTimeStampDeq
}

trait InterfaceStat{ this: InterfaceBase =>

  val statDownRecErrorCnt          = RegInit(0.U(32.W)); cReg.statDownRecErrorCnt          := statDownRecErrorCnt
  val statDownRecHeaderErrorCnt    = RegInit(0.U(16.W)); cReg.statDownRecHeaderErrorCnt    := statDownRecHeaderErrorCnt
  val statDownRecSubHeaderErrorCnt = RegInit(0.U(16.W)); cReg.statDownRecSubHeaderErrorCnt := statDownRecSubHeaderErrorCnt
  val statDownRecPayloadErrorCnt   = RegInit(0.U(16.W)); cReg.statDownRecPayloadErrorCnt   := statDownRecPayloadErrorCnt
  val statDownRecSubTailErrorCnt   = RegInit(0.U(16.W)); cReg.statDownRecSubTailErrorCnt   := statDownRecSubTailErrorCnt
  val statDownRecCRCErrorCnt       = RegInit(0.U(16.W)); cReg.statDownRecCRCErrorCnt       := statDownRecCRCErrorCnt
  val statDownRecFinishCnt         = RegInit(0.U(32.W)); cReg.statDownRecFinishCnt         := statDownRecFinishCnt
  val statDownRecByteCnt           = RegInit(0.U(64.W)); cReg.statDownRecByteCnt           := statDownRecByteCnt

  val statUpRecErrorCnt          = RegInit(0.U(32.W)); cReg.statUpRecErrorCnt          := statUpRecErrorCnt
  val statUpRecHeaderErrorCnt    = RegInit(0.U(16.W)); cReg.statUpRecHeaderErrorCnt    := statUpRecHeaderErrorCnt
  val statUpRecSubHeaderErrorCnt = RegInit(0.U(16.W)); cReg.statUpRecSubHeaderErrorCnt := statUpRecSubHeaderErrorCnt
  val statUpRecPayloadErrorCnt   = RegInit(0.U(16.W)); cReg.statUpRecPayloadErrorCnt   := statUpRecPayloadErrorCnt
  val statUpRecSubTailErrorCnt   = RegInit(0.U(16.W)); cReg.statUpRecSubTailErrorCnt   := statUpRecSubTailErrorCnt
  val statUpRecCRCErrorCnt       = RegInit(0.U(16.W)); cReg.statUpRecCRCErrorCnt       := statUpRecCRCErrorCnt
  val statUpRecFinishCnt         = RegInit(0.U(32.W)); cReg.statUpRecFinishCnt         := statUpRecFinishCnt
  val statUpRecByteCnt           = RegInit(0.U(64.W)); cReg.statUpRecByteCnt           := statUpRecByteCnt



  when(io.lvds.isEnW & (io.lvds.addrw === "h80".U )){
    statDownRecErrorCnt := 0.U
  } .elsewhen( io.downRecStat.isRecError ){
    statDownRecErrorCnt := statDownRecErrorCnt + 1.U
  }

  when(io.lvds.isEnW & (io.lvds.addrw === "h82".U )){
    statDownRecHeaderErrorCnt := 0.U
  } .elsewhen( io.downRecStat.isHeaderError ){
    statDownRecHeaderErrorCnt := statDownRecHeaderErrorCnt + 1.U
  }

  when(io.lvds.isEnW & (io.lvds.addrw === "h84".U )){
    statDownRecSubHeaderErrorCnt := 0.U
  } .elsewhen( io.downRecStat.isSubHeaderError ){
    statDownRecSubHeaderErrorCnt := statDownRecSubHeaderErrorCnt + 1.U
  }

  when(io.lvds.isEnW & (io.lvds.addrw === "h86".U )){
    statDownRecPayloadErrorCnt := 0.U
  } .elsewhen( io.downRecStat.isPayloadError ){
    statDownRecPayloadErrorCnt := statDownRecPayloadErrorCnt + 1.U
  }

  when(io.lvds.isEnW & (io.lvds.addrw === "h88".U )){
    statDownRecSubTailErrorCnt := 0.U
  } .elsewhen( io.downRecStat.isSubTailError ){
    statDownRecSubTailErrorCnt := statDownRecSubTailErrorCnt + 1.U
  }

  when(io.lvds.isEnW & (io.lvds.addrw === "h8a".U )){
    statDownRecCRCErrorCnt := 0.U
  } .elsewhen( io.downRecStat.isCRCError ){
    statDownRecCRCErrorCnt := statDownRecCRCErrorCnt + 1.U
  }

  when(io.lvds.isEnW & (io.lvds.addrw === "h8c".U )){
    statDownRecFinishCnt := 0.U
  } .elsewhen( io.downRecStat.isFinish ){
    statDownRecFinishCnt := statDownRecFinishCnt + 1.U
  }

  when(io.lvds.isEnW & (io.lvds.addrw === "h90".U )){
    statDownRecByteCnt := 0.U
  } .elsewhen( io.downRecStat.isRecByteAck ){
    statDownRecByteCnt := statDownRecByteCnt + 1.U
  }






  when(io.lvds.isEnW & (io.lvds.addrw === "ha0".U )){
    statUpRecErrorCnt := 0.U
  } .elsewhen( io.upRecStat.isRecError ){
    statUpRecErrorCnt := statUpRecErrorCnt + 1.U
  }

  when(io.lvds.isEnW & (io.lvds.addrw === "ha2".U )){
    statUpRecHeaderErrorCnt := 0.U
  } .elsewhen( io.upRecStat.isHeaderError ){
    statUpRecHeaderErrorCnt := statUpRecHeaderErrorCnt + 1.U
  }

  when(io.lvds.isEnW & (io.lvds.addrw === "ha4".U )){
    statUpRecSubHeaderErrorCnt := 0.U
  } .elsewhen( io.upRecStat.isSubHeaderError ){
    statUpRecSubHeaderErrorCnt := statUpRecSubHeaderErrorCnt + 1.U
  }

  when(io.lvds.isEnW & (io.lvds.addrw === "ha6".U )){
    statUpRecPayloadErrorCnt := 0.U
  } .elsewhen( io.upRecStat.isPayloadError ){
    statUpRecPayloadErrorCnt := statUpRecPayloadErrorCnt + 1.U
  }

  when(io.lvds.isEnW & (io.lvds.addrw === "ha8".U )){
    statUpRecSubTailErrorCnt := 0.U
  } .elsewhen( io.upRecStat.isSubTailError ){
    statUpRecSubTailErrorCnt := statUpRecSubTailErrorCnt + 1.U
  }

  when(io.lvds.isEnW & (io.lvds.addrw === "haa".U )){
    statUpRecCRCErrorCnt := 0.U
  } .elsewhen( io.upRecStat.isCRCError ){
    statUpRecCRCErrorCnt := statUpRecCRCErrorCnt + 1.U
  }

  when(io.lvds.isEnW & (io.lvds.addrw === "hac".U )){
    statUpRecFinishCnt := 0.U
  } .elsewhen( io.upRecStat.isFinish ){
    statUpRecFinishCnt := statUpRecFinishCnt + 1.U
  }

  when(io.lvds.isEnW & (io.lvds.addrw === "hb0".U )){
    statUpRecByteCnt := 0.U
  } .elsewhen( io.upRecStat.isRecByteAck ){
    statUpRecByteCnt := statUpRecByteCnt + 1.U
  }


}



class Interface extends InterfaceBase
with InterfaceMCUop
with InterfaceCheckSM
with InterfaceLVDSop
with InterfaceSync
with InterfaceStat
with InterfaceWdt
with InterfaceSystem
with InterfaceEvent
{


  io.txReq.bits.txSM  := mReg.txSM
  io.txReq.bits.rxSM  := mReg.rxSM
  // io.txReq.bits.txLength := //mReg.txLength
  io.txReq.valid := RegNext(isEnW & addrw === "h20".U & dataw.extract(0) === "b1".U, false.B) //& mReg.txLength =/= 0.U




  sReg.localDevIndex := io.localDevIndex

  // sReg.isDevOnLeft        := io.isDevOnLeft
  // sReg.isDevOnLeftModify  := io.isDevOnLeftModify
  // sReg.indexOfLeftDev     := io.indexOfLeftDev
  sReg.isDevOnRight       := io.isDevOnRight
  sReg.isDevOnRightModify := io.isDevOnRightModify
  sReg.indexOfRightDev    := io.indexOfRightDev



}