eb001/src/main/scala/backBoard/shin/Interface.scala

package BACK

import chisel3._
import chisel3.util._

class CommonRegisterBundle extends Bundle{
  val mstOrSlv  = UInt(2.W)
  val hwVersion = UInt(8.W)
  val hwSerial  = UInt(48.W)
  val busRate   = UInt(16.W)

  // val spiSel       = UInt(2.W)

  // val isSoftReset  = Bool()
  val encryptKey   = UInt(128.W)
  val isEncrypt    = Bool()

  // val upRecErrorCnt   = UInt(32.W)
  // val downRecErrorCnt = UInt(32.W)
  // val upForwardErrorCnt   = UInt(32.W)
  // val downForwardErrorCnt = UInt(32.W)

  // val qspiErrorCnt   = UInt(32.W)
  // val forwardCnt     = UInt(32.W)
  // val recByteCnt     = UInt(32.W)
  // val forwardByteCnt = UInt(32.W)


  // val wdtStatus   = UInt(16.W)
  // val wdtOverflow = UInt(8.W)

  val timeStamp = UInt(64.W)
  val deltaTime = UInt(32.W)

  val linkStatus = UInt(8.W)


  val smEnqAddr = Vec(8, UInt(11.W)) //触发SM切换缓冲区的地址 （或读或写）
  val smDeqAddr = Vec(8, UInt(11.W)) //触发SM切换缓冲区的地址 （或读或写）



}

class MasterRegisterBundle extends Bundle{


  val txSM         = UInt(2.W)
  val txStatus     = UInt(16.W)


  val intEnable    = UInt(8.W)
  val intMask      = UInt(8.W)
  val intStatus    = UInt(8.W)

}


class SlaveRegisterBundle extends Bundle{

  val RAMSize   = UInt(8.W)
  val MMUNum    = UInt(8.W)

  val nodeSeqAddr = UInt(16.W)
  val nodeSetAddr = UInt(16.W)


  val ebmmu = Vec(8, new Bundle{
    val logicAddr = UInt(32.W)
    val length = UInt(16.W)
    val phyAddr = UInt(32.W)
    val op = UInt(2.W)
    val enable = Bool()
  })

  val intStatus = UInt(16.W)
  val mb = Vec(8, new Bundle{
    val ctrl = UInt(8.W)
    val status = UInt(8.W)
  })


  val downTimeStamp = UInt(64.W) //下行本地时间戳寄存器 
  val upTimeStamp   = UInt(64.W) //上行本地时间戳寄存器
  val mstTimeStamp  = UInt(64.W) //主站时间戳

  val dcSyncEnable = Bool()
  val dcSyncWidth  = UInt(16.W)
}



class InterfaceIO extends Bundle{
  val ospi = new SPIInterfaceIO

  // val req = Valid(new Bundle{
  //   val addr = UInt(16.W)
  //   val dataw = UInt(8.W)
  //   val isWRn = Bool()
  // })

  // val resp = Valid(new Bundle{
  //   datar = UInt(8.W)
  // })

  val modeSel = Output(Bool())

  val txReq = Valid(new Bundle{
    val txSM = UInt(2.W)
    val rxSM = UInt(2.W)
  }) //发送请求和SM代号


  val dSMdeq = Output( Vec(4, Bool()) )
  val uSMenq = Output( Vec(4, Bool()) )

  val sram_w = Flipped(Vec( 4, new SRAM2kWRIO)) //QSPI
  val sram_r = Flipped(Vec( 4, new SRAM2kRDIO)) //QSPI


}


abstract class InterfaceBase extends Module{
  val io: InterfaceIO = IO(new InterfaceIO)

  val oSpi = Module(new SpiInterface)
  io.ospi <> oSpi.io.spi

  val cReg = Wire(new CommonRegisterBundle)
  val mReg = Wire(new MasterRegisterBundle)
  val sReg = Wire(new SlaveRegisterBundle)

  val isSysInit = cReg.mstOrSlv =/= 0.U

  def AcquireReg(addr: UInt): UInt = {
    Mux1H(
      Seq(
      (addr === "h0".U) -> cReg.mstOrSlv,
      (addr === "h1".U) -> cReg.hwVersion,
      ) ++

      ((0 until 6).map{ i =>
        (addr === ("h2".U + i.U) ) -> cReg.hwSerial( 8*i+7,8*i+0),
      }) ++
      
      Seq(
        (addr === "h8".U) -> cReg.busRate( 7,0),
        (addr === "h9".U) -> cReg.busRate(15,8),        
      ) ++

      ((0 until 16).map{ i =>
        (addr === ("h80".U + i.U) ) -> cReg.encryptKey( 8*i+7,8*i+0),
      }) ++

      Seq()

    )
  }


    



}

trait InterfaceMCUop{ this: InterfaceBase =>



  oSpi.io.addrSel = Output(UInt(16.W))
  oSpi.io.dataw   = Output( UInt(8.W) )
  oSpi.io.datar   :=
    MuxCase( 0.U, Array(
      ((oSpi.io.addrSel & "hFF00".U) === "h0000".U) -> RegEnable( AcquireReg(addr = oSpi.io.addrSel), 0.U, oSpi.io.isEnR ),
      ((oSpi.io.addrSel & "hFF00".U) === "h0800".U) -> smUnit(0).io.sram_r.datar,
      ((oSpi.io.addrSel & "hFF00".U) === "h1000".U) -> 0.U,
      ((oSpi.io.addrSel & "hFF00".U) === "h1800".U) -> smUnit(2).io.sram_r.datar,
      ((oSpi.io.addrSel & "hFF00".U) === "h2000".U) -> 0.U,
      ((oSpi.io.addrSel & "hFF00".U) === "h2800".U) -> smUnit(4).io.sram_r.datar,
      ((oSpi.io.addrSel & "hFF00".U) === "h3000".U) -> 0.U,
      ((oSpi.io.addrSel & "hFF00".U) === "h3800".U) -> smUnit(6).io.sram_r.datar,
      ((oSpi.io.addrSel & "hFF00".U) === "h4000".U) -> 0.U,
    ))

  oSpi.io.isEnW   = Output(Bool())

  val isEnW = oSpi.io.isEnW
  val addrSel = oSpi.io.addrSel
  val dataw = oSpi.io.dataw
  val isEnR = oSpi.io.isEnR

  cReg.mstOrSlv  := RegEnable( dataw(1,0), 0.U, isEnW & addrSel === "h0".U & cReg.mstOrSlv === 0.U )
  cReg.hwVersion := RegEnable( dataw     , 0.U, isEnW & addrSel === "h1".U & cReg.mstOrSlv === 0.U )

  cReg.hwSerial := 
    Cat(
      (0 until 6).map{ i =>
      RegEnable( dataw, 0.U, isEnW & addrSel === ("h2".U + i.U) & cReg.mstOrSlv === 0.U )
      }.reverse
    )
  
  cReg.busRate :=
    Cat(
      RegEnable( dataw, 0.U, isEnW & addrSel === "h9".U & cReg.mstOrSlv === 0.U ),
      RegEnable( dataw, 0.U, isEnW & addrSel === "h8".U & cReg.mstOrSlv === 0.U )
    )

  cReg.encryptKey :=
    Cat(
      (0 until 16).map{ i =>
        RegEnable( dataw, 0.U, isEnW & addrSel === ("h80".U + i.U) & cReg.mstOrSlv === 0.U )
      }.reserve
    )
















}

trait InterfaceCheckSM{ this: InterfaceBase =>
  mReg.txSM := RegEnable( dataw(2,1), 0.U, isEnW & addrSel === "h20".U )
  mReg.rxSM := RegEnable( dataw(4,3), 0.U, isEnW & addrSel === "h20".U )

  for( i <- 0 until 8 ){
    cReg.smEnqAddr(i) := 
      Cat(
        RegEnable( dataw, 0.U, isEnW & addrSel === "h20".U ),
        RegEnable( dataw, 0.U, isEnW & addrSel === "h20".U )
      )
    cReg.smDeqAddr(i) := 
      Cat(
        RegEnable( dataw, 0.U, isEnW & addrSel === "h20".U ),
        RegEnable( dataw, 0.U, isEnW & addrSel === "h20".U )
      )
  }


  io.sram_r(0).addrr := addrSel
  io.sram_r(1).addrr := addrSel
  io.sram_r(2).addrr := addrSel
  io.sram_r(3).addrr := addrSel

  io.sram_r(0).enr   := isEnR & (( addrSel & "hF800".U ) === "h0800".U)
  io.sram_r(1).enr   := isEnR & (( addrSel & "hF800".U ) === "h1800".U)
  io.sram_r(2).enr   := isEnR & (( addrSel & "hF800".U ) === "h2800".U)
  io.sram_r(3).enr   := isEnR & (( addrSel & "hF800".U ) === "h3800".U)

  io.sram_w(0).addrw := addrSel
  io.sram_w(1).addrw := addrSel
  io.sram_w(2).addrw := addrSel
  io.sram_w(3).addrw := addrSel

  io.sram_w(0).dataw := dataw
  io.sram_w(1).dataw := dataw
  io.sram_w(2).dataw := dataw
  io.sram_w(3).dataw := dataw

  io.sram_w(0).enw   := isEnW & (( addrSel & "hF800".U ) === "h1000".U)
  io.sram_w(1).enw   := isEnW & (( addrSel & "hF800".U ) === "h2000".U)
  io.sram_w(2).enw   := isEnW & (( addrSel & "hF800".U ) === "h3000".U)
  io.sram_w(3).enw   := isEnW & (( addrSel & "hF800".U ) === "h4000".U)

  io.dSMdeq(0) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === smDeqAddr(0))
  io.dSMdeq(1) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === smDeqAddr(2))
  io.dSMdeq(2) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === smDeqAddr(4))
  io.dSMdeq(3) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === smDeqAddr(6))

  io.uSMenq(0) := isEnW & (( addrSel & "hF800".U ) === "h1000".U) & (addrSel(10,0) === smEnqAddr(1))
  io.uSMenq(1) := isEnW & (( addrSel & "hF800".U ) === "h2000".U) & (addrSel(10,0) === smEnqAddr(3))
  io.uSMenq(2) := isEnW & (( addrSel & "hF800".U ) === "h3000".U) & (addrSel(10,0) === smEnqAddr(5))
  io.uSMenq(3) := isEnW & (( addrSel & "hF800".U ) === "h4000".U) & (addrSel(10,0) === smEnqAddr(7))
}

trait InterfaceLVDSop{ this: InterfaceBase =>

}



class Interface extends InterfaceBase
with InterfaceMCUop
{

  io.modeSel := cReg.mstOrSlv === "h1".U

  io.txReq.bits.txSM  := mReg.txSM
  io.txReq.bits.rxSM  := mReg.rxSM
  io.txReq.valid := isEnW & addrSel === "h20".U & dataw.extract(0) === "b1".U

}