eb001/src/main/scala/backBoard/shin/Interface.scala

package BACK

import chisel3._
import chisel3.util._

class CommonRegisterBundle extends Bundle{
  val mstOrSlv  = UInt(2.W)
  def modeSel:Bool = mstOrSlv === "h1".U

  val hwVersion = UInt(8.W)
  val hwSerial  = UInt(48.W)
  val busRate   = UInt(8.W)

  val spiSel    = UInt(2.W)

  val encryptKey   = UInt(128.W)
  val isEncrypt    = Bool()

  // val upRecErrorCnt   = UInt(32.W)
  // val downRecErrorCnt = UInt(32.W)
  // val upForwardErrorCnt   = UInt(32.W)
  // val downForwardErrorCnt = UInt(32.W)

  // val qspiErrorCnt   = UInt(32.W)
  // val forwardCnt     = UInt(32.W)
  // val recByteCnt     = UInt(32.W)
  // val forwardByteCnt = UInt(32.W)



  // val wdtStatus   = UInt(16.W)
  // val wdtOverflow = UInt(8.W)

  val timeStamp = UInt(64.W)
  val mstDeltaTime = UInt(32.W)

  val syncPoint = UInt(64.W)
  val syncPeroid = UInt(32.W)

  val custom = Vec( 128, UInt(8.W) )


  // val smEnqAddr = Vec(8, UInt(11.W)) //触发SM切换缓冲区的地址 （或读或写）
  // val smDeqAddr = Vec(8, UInt(11.W)) //触发SM切换缓冲区的地址 （或读或写）
  val smTrigLen = Vec(8, UInt(11.W))  //触发SM切换缓冲区的地址 （或读或写）


}

class MasterRegisterBundle extends Bundle{


  val txSM         = UInt(2.W)
  val rxSM         = UInt(2.W)
  // val txLength     = UInt(12.W)
  // val txStatus     = UInt(16.W)

  val rplTimeStampTx = UInt(16.W)


  // val intEnable    = UInt(8.W)
  // val intMask      = UInt(8.W)
  // val intStatus    = UInt(8.W)

}


class SlaveRegisterBundle extends Bundle{

  // val RAMSize   = UInt(8.W)
  // val MMUNum    = UInt(8.W)

  // val nodeSeqAddr = UInt(16.W)
  // val nodeSetAddr = UInt(16.W)


  // val ebmmu = Vec(8, new Bundle{
  //   val logicAddr = UInt(32.W)
  //   val length = UInt(16.W)
  //   val phyAddr = UInt(32.W)
  //   val op = UInt(2.W)
  //   val enable = Bool()
  // })

  // val intStatus = UInt(16.W)
  // val mb = Vec(8, new Bundle{
  //   val ctrl = UInt(8.W)
  //   val status = UInt(8.W)
  // })





  val localDevIndex = UInt(16.W)

  //链路寄存器组

  // val isDevOnLeftModify = Bool()
  // val indexOfLeftDev = UInt(14.W)
  val isDevOnRight = UInt(2.W)
  val isDevOnRightModify = Bool()
  val indexOfRightDev = UInt(14.W)


  val slvDeltaTime  = UInt(32.W) //从站时间戳差值
  val deltaFinal    = UInt(32.W) //当前时间戳与主站时间差
  val recoTimeStamp = UInt(64.W) //时钟补偿寄存器

  val syncCfg = UInt(8.W)
  val syncWidth = Vec(4, UInt(16.W) )



  val syncOffset = Vec(4, UInt(32.W))





}



class InterfaceIO extends Bundle{
  val ospi = new SSPIInterfaceIO
  val oqspi = new QSPIInterfaceIO
  val iqspi = new QSPIInterfaceIO

  val lvds  = Flipped(new RegAccessInterfaceIO)



  // val modeSel = Output(Bool())

  val txReq = Valid(new Bundle{
    val txSM = UInt(2.W)
    val rxSM = UInt(2.W)
    // val txLength = UInt(12.W)
  }) //发送请求和SM代号


  val dSMdeq = Output( Vec(4, Bool()) )
  val uSMenq = Output( Vec(4, Bool()) )

  val sram_w = Flipped(Vec( 4, new SRAM2kWRIO)) //QSPI
  val sram_r = Flipped(Vec( 4, new SRAM2kRDIO)) //QSPI

  val cReg = Output(new CommonRegisterBundle)
  val mReg = Output(new MasterRegisterBundle)
  val sReg = Output(new SlaveRegisterBundle)

  val localDevIndex = Input(UInt(16.W))

  // val isDevOnLeft = Input(UInt(2.W))
  // val isDevOnLeftModify = Input(Bool())
  // val indexOfLeftDev = Input(UInt(14.W))

  val isDevOnRight = Input(UInt(2.W))
  val isDevOnRightModify = Input(Bool())
  val indexOfRightDev = Input(UInt(14.W))



  val slvDeltaTime  = Input(UInt(32.W)) //从站时间戳差值
  val mstDeltaTime  = Input(UInt(32.W))
  val deltaFinal = Input(UInt(32.W))

  val sync = Output(Vec(4, Bool()))

  val initEncryptor = Valid(UInt(128.W))

  val isSoftReset = Output(Bool())
}


abstract class InterfaceBase extends Module{
  val io: InterfaceIO = IO(new InterfaceIO)

  val oSpi  = Module(new SSpiInterface)
  val oQSpi = Module(new QSpiInterface)
  val iQSpi = Module(new QSpiInterface)

  io.ospi <> oSpi.spi
  io.oqspi <> oQSpi.qspi
  io.iqspi <> iQSpi.qspi

  val cReg = Wire(new CommonRegisterBundle); io.cReg := cReg
  val mReg = Wire(new MasterRegisterBundle); io.mReg := mReg
  val sReg = Wire(new SlaveRegisterBundle);  io.sReg := sReg

  val syncCfg = RegInit(0.U(8.W)); sReg.syncCfg := syncCfg

  val syncWidth = for( i <- 0 until 4 ) yield { RegInit(0.U(16.W)) }
  for( i <- 0 until 4 ) {
    sReg.syncWidth(i) := syncWidth(i)
  }

  val syncPoint   = RegInit(0.U(64.W)); cReg.syncPoint := syncPoint
  val syncPeroid  = RegInit(0.U(32.W)); cReg.syncPeroid := syncPeroid

  val syncOffset = for( i <- 0 until 4 ) yield { RegInit(0.U(32.W)) } //空开0
  for( i <- 0 until 4 ) {
    sReg.syncOffset(i) := syncOffset(i)
  }




  val isSysInit = cReg.mstOrSlv =/= 0.U
  val isMstMode = cReg.mstOrSlv === "h1".U
  val isSlvMode = cReg.mstOrSlv === "h2".U

  def AcquireReg(addr: UInt): UInt = {
    Mux1H(
      Seq(
      (addr === "h0".U) -> cReg.mstOrSlv,
      (addr === "h1".U) -> cReg.hwVersion,
      ) ++

      ((0 until 6).map{ i =>
        (addr === ("h2".U + i.U) ) -> cReg.hwSerial( 8*i+7,8*i+0 )
      }) ++
      
      Seq(
        (addr === "h8".U )  -> cReg.busRate( 7,0 ),
        (addr === "h9".U )  -> cReg.spiSel,
        (addr === "ha".U & isSlvMode)  -> sReg.localDevIndex(7,0),
        (addr === "hb".U & isSlvMode)  -> sReg.localDevIndex(15,8),


        (addr === "h20".U & isMstMode) -> Cat(mReg.rxSM, mReg.txSM, 0.U(1.W) ),
                //(addr === "h21".U & isMstMode) -> mReg.txLength,

        (addr === "h24".U & isMstMode) -> mReg.rplTimeStampTx(7,0),
        (addr === "h25".U & isMstMode) -> mReg.rplTimeStampTx(15,8),



      ) ++





      ((0 until 16).map{ i =>
        (addr === ("h50".U + i.U) ) -> cReg.encryptKey( 8*i+7,8*i+0 )
      }) ++

      Seq(
        (addr === "h60".U ) -> cReg.isEncrypt,
        (addr === "hc0".U ) -> Cat( sReg.isDevOnRightModify, sReg.isDevOnRight, 0.U(3.W) ),
        (addr === "hc2".U ) -> sReg.indexOfRightDev(7,0),
        (addr === "hc3".U ) -> sReg.indexOfRightDev(13,8),
        // (addr === "hc4".U ) -> sReg.indexOfLeftDev(7,0),
        // (addr === "hc5".U ) -> sReg.indexOfLeftDev(13,8),
      ) ++

      Seq(
        //本地时钟
        (addr === "h100".U )  -> cReg.timeStamp(7,0),
        (addr === "h101".U )  -> cReg.timeStamp(15,8),
        (addr === "h102".U )  -> cReg.timeStamp(23,16),
        (addr === "h103".U )  -> cReg.timeStamp(31,24),
        (addr === "h104".U )  -> cReg.timeStamp(39,32),
        (addr === "h105".U )  -> cReg.timeStamp(47,40),
        (addr === "h106".U )  -> cReg.timeStamp(55,48),
        (addr === "h107".U )  -> cReg.timeStamp(63,56),

        //参考主站时钟
        (addr === "h108".U & isSlvMode)  -> sReg.deltaFinal(7,0),
        (addr === "h109".U & isSlvMode)  -> sReg.deltaFinal(15,8),
        (addr === "h10a".U & isSlvMode)  -> sReg.deltaFinal(23,16),
        (addr === "h10b".U & isSlvMode)  -> sReg.deltaFinal(31,24),
        // (addr === "h10c".U & isSlvMode)  -> sReg.deltaFinal(39,32),
        // (addr === "h10d".U & isSlvMode)  -> sReg.deltaFinal(47,40),
        // (addr === "h10e".U & isSlvMode)  -> sReg.deltaFinal(55,48),
        // (addr === "h10f".U & isSlvMode)  -> sReg.deltaFinal(63,56),

        //主站发送接收时间差
        (addr === "h110".U )  -> cReg.mstDeltaTime(7,0),  
        (addr === "h111".U )  -> cReg.mstDeltaTime(15,8), 
        (addr === "h112".U )  -> cReg.mstDeltaTime(23,16),
        (addr === "h113".U )  -> cReg.mstDeltaTime(31,24),

        //从站发送接收时间差
        (addr === "h114".U & isSlvMode)  -> sReg.slvDeltaTime(7,0),  
        (addr === "h115".U & isSlvMode)  -> sReg.slvDeltaTime(15,8), 
        (addr === "h116".U & isSlvMode)  -> sReg.slvDeltaTime(23,16),
        (addr === "h117".U & isSlvMode)  -> sReg.slvDeltaTime(31,24),

        //校准后的时钟
        (addr === "h118".U & isSlvMode)  -> sReg.recoTimeStamp(7,0),
        (addr === "h119".U & isSlvMode)  -> sReg.recoTimeStamp(15,8),
        (addr === "h11a".U & isSlvMode)  -> sReg.recoTimeStamp(23,16),
        (addr === "h11b".U & isSlvMode)  -> sReg.recoTimeStamp(31,24),
        (addr === "h11c".U & isSlvMode)  -> sReg.recoTimeStamp(39,32),
        (addr === "h11d".U & isSlvMode)  -> sReg.recoTimeStamp(47,40),
        (addr === "h11e".U & isSlvMode)  -> sReg.recoTimeStamp(55,48),
        (addr === "h11f".U & isSlvMode)  -> sReg.recoTimeStamp(63,56),

        (addr === "h120".U & isSlvMode)  -> sReg.syncCfg,

        (addr === "h122".U & isSlvMode)  -> sReg.syncWidth(0)(7,0),
        (addr === "h123".U & isSlvMode)  -> sReg.syncWidth(0)(15,8),

        (addr === "h124".U & isSlvMode)  -> sReg.syncWidth(1)(7,0),
        (addr === "h125".U & isSlvMode)  -> sReg.syncWidth(1)(15,8),

        (addr === "h126".U & isSlvMode)  -> sReg.syncWidth(2)(7,0),
        (addr === "h127".U & isSlvMode)  -> sReg.syncWidth(2)(15,8),

        (addr === "h128".U & isSlvMode)  -> sReg.syncWidth(3)(7,0),
        (addr === "h129".U & isSlvMode)  -> sReg.syncWidth(3)(15,8),

        (addr === "h130".U )  -> cReg.syncPoint(7,0),
        (addr === "h131".U )  -> cReg.syncPoint(15,8),
        (addr === "h132".U )  -> cReg.syncPoint(23,16),
        (addr === "h133".U )  -> cReg.syncPoint(31,24),
        (addr === "h134".U )  -> cReg.syncPoint(39,32),
        (addr === "h135".U )  -> cReg.syncPoint(47,40),
        (addr === "h136".U )  -> cReg.syncPoint(55,48),
        (addr === "h137".U )  -> cReg.syncPoint(63,56),

        (addr === "h138".U )  -> cReg.syncPeroid(7,0),
        (addr === "h139".U )  -> cReg.syncPeroid(15,8),
        (addr === "h13a".U )  -> cReg.syncPeroid(23,16),
        (addr === "h13b".U )  -> cReg.syncPeroid(31,24),

        (addr === "h13c".U & isSlvMode)  -> sReg.syncOffset(1)(7,0),
        (addr === "h13d".U & isSlvMode)  -> sReg.syncOffset(1)(15,8),
        (addr === "h13e".U & isSlvMode)  -> sReg.syncOffset(1)(23,16),
        (addr === "h13f".U & isSlvMode)  -> sReg.syncOffset(1)(31,24),

        (addr === "h140".U & isSlvMode)  -> sReg.syncOffset(2)(7,0),
        (addr === "h141".U & isSlvMode)  -> sReg.syncOffset(2)(15,8),
        (addr === "h142".U & isSlvMode)  -> sReg.syncOffset(2)(23,16),
        (addr === "h143".U & isSlvMode)  -> sReg.syncOffset(2)(31,24),

        (addr === "h144".U & isSlvMode)  -> sReg.syncOffset(3)(7,0),
        (addr === "h145".U & isSlvMode)  -> sReg.syncOffset(3)(15,8),
        (addr === "h146".U & isSlvMode)  -> sReg.syncOffset(3)(23,16),
        (addr === "h147".U & isSlvMode)  -> sReg.syncOffset(3)(31,24),
      ) ++
      ( 0 until 128 ).map{ i =>
        ( addr === ("h180".U + i.U )   ) -> cReg.custom(i)
      } ++
      ( 0 until 8 ).map{ i =>
        ( addr === ("h302".U + (i*4).U) )  -> cReg.smTrigLen(i)(7,0)
      } ++
      ( 0 until 8 ).map{ i =>
        ( addr === ("h303".U + (i*4).U) )  -> cReg.smTrigLen(i)(10,8)
      } ++
      Seq()
    )


  }



  //spi信号
  val addrr = Wire(UInt(16.W))
  val addrw = Wire(UInt(16.W))
  val dataw   = Wire( UInt(8.W) )
  val datar   = Wire( UInt(8.W) )  
  val isEnW = Wire(Bool())
  val isEnR = Wire(Bool())


}

trait InterfaceMCUop{ this: InterfaceBase =>







  isEnW := Mux1H(Seq(
    ( cReg.spiSel === 0.U ) -> iQSpi.io.isEnW,
    ( cReg.spiSel === 1.U ) ->  oSpi.io.isEnW,
    ( cReg.spiSel === 2.U ) -> oQSpi.io.isEnW,
  ))
    
  addrr := Mux1H(Seq(
    ( cReg.spiSel === 0.U ) -> iQSpi.io.addrr,
    ( cReg.spiSel === 1.U ) ->  oSpi.io.addrr,
    ( cReg.spiSel === 2.U ) -> oQSpi.io.addrr,
  ))

  addrw := Mux1H(Seq(
    ( cReg.spiSel === 0.U ) -> iQSpi.io.addrw,
    ( cReg.spiSel === 1.U ) ->  oSpi.io.addrw,
    ( cReg.spiSel === 2.U ) -> oQSpi.io.addrw,
  ))

  dataw := Mux1H(Seq(
    ( cReg.spiSel === 0.U ) -> iQSpi.io.dataw,
    ( cReg.spiSel === 1.U ) ->  oSpi.io.dataw,
    ( cReg.spiSel === 2.U ) -> oQSpi.io.dataw,
  ))

  isEnR := Mux1H(Seq(
    ( cReg.spiSel === 0.U ) -> iQSpi.io.isEnR,
    ( cReg.spiSel === 1.U ) ->  oSpi.io.isEnR,
    ( cReg.spiSel === 2.U ) -> oQSpi.io.isEnR,
  ))

  datar := MuxCase( 0.U, Array(
      ((addrr & "hF800".U) === "h0000".U) -> RegEnable( AcquireReg(addr = addrr), isEnR ),
      ((addrr & "hF800".U) === "h0800".U) -> io.sram_r(0).datar,
      ((addrr & "hF800".U) === "h1000".U) -> 0.U,
      ((addrr & "hF800".U) === "h1800".U) -> io.sram_r(1).datar,
      ((addrr & "hF800".U) === "h2000".U) -> 0.U,
      ((addrr & "hF800".U) === "h2800".U) -> io.sram_r(2).datar,
      ((addrr & "hF800".U) === "h3000".U) -> 0.U,
      ((addrr & "hF800".U) === "h3800".U) -> io.sram_r(3).datar,
      ((addrr & "hF800".U) === "h4000".U) -> 0.U,
    ))

  iQSpi.io.datar := Mux(cReg.spiSel === 0.U, datar, 0.U)
   oSpi.io.datar := Mux(cReg.spiSel === 1.U, datar, 0.U)
  oQSpi.io.datar := Mux(cReg.spiSel === 2.U, datar, 0.U)

  when( isEnW ){
    printf(s"SPI/QSPI Write 0x%x, @0x%x\n", dataw, addrw)
  }
  when( isEnR ){
    printf(s"SPI/QSPI Readout 0x%x, @0x%x\n", datar, addrr)
  }



  cReg.mstOrSlv  := RegEnable( dataw(1,0), 0.U, isEnW & addrw === "h0".U & cReg.mstOrSlv === 0.U )
  cReg.hwVersion := RegEnable( dataw     , "hF0".U, isEnW & addrw === "h1".U & cReg.mstOrSlv === 0.U )

  cReg.hwSerial := 
    Cat(
      (0 until 6).map{ i =>
      RegEnable( dataw, "haa".U, isEnW & addrw === ("h2".U + i.U) & cReg.mstOrSlv === 0.U )
      }.reverse
    )
  
  cReg.busRate := RegEnable( dataw, "h55".U, isEnW & addrw === "h8".U & cReg.mstOrSlv === 0.U )
  cReg.spiSel  := RegEnable( dataw(1,0), 0.U, isEnW & addrw === "h9".U & cReg.mstOrSlv === 0.U )

  cReg.encryptKey :=
    Cat(
      (0 until 16).map{ i =>
        RegEnable( dataw, 0.U, isEnW & addrw === ("h50".U + i.U) & cReg.mstOrSlv === 0.U )
      }.reverse
    )

  cReg.isEncrypt := RegEnable( dataw.extract(0), 0.U, isEnW & addrw === "h60".U & cReg.mstOrSlv === 0.U )

  mReg.txSM     := RegEnable( dataw(2,1), 0.U, isEnW & addrw === "h20".U )
  mReg.rxSM     := RegEnable( dataw(4,3), 0.U, isEnW & addrw === "h20".U )
  // mReg.txLength := Cat( RegEnable( dataw, 0.U, isEnW & addrw === "h22".U ), RegEnable( dataw, 0.U, isEnW & addrw === "h21".U ) )

  ( 0 until 128 ).map{ i =>
    cReg.custom(i) := RegEnable( dataw, 0.U, isEnW & (addrw === ("h180".U + i.U)) )
  }




  mReg.rplTimeStampTx := 
    Cat(
      RegEnable( dataw, 0.U, isEnW & addrw === "h25".U ),
      RegEnable( dataw, 0.U, isEnW & addrw === "h24".U )
    )


  when( isEnW & isSlvMode ){
    when( addrw === "h120".U ){
      syncCfg := dataw
    }

    for( i <- 0 until 4 ){
      when( io.lvds.addrw === ("h122".U + (2*i).U)){
        syncWidth(i) := Cat( syncWidth(i)(15,8), io.lvds.dataw ) 
      } .elsewhen( io.lvds.addrw === ("h123".U + (2*i).U) ){
        syncWidth(i) := Cat( io.lvds.dataw, syncWidth(i)(7,0) ) 
      }
    }

    when( addrw === "h130".U ){
      syncPoint := Cat( syncPoint(63,8), dataw ) 
    } .elsewhen( addrw === "h131".U ){
      syncPoint := Cat( syncPoint(63,16), dataw, syncPoint(7,0) ) 
    } .elsewhen( addrw === "h132".U ){
      syncPoint := Cat( syncPoint(63,24), dataw, syncPoint(15,0) ) 
    } .elsewhen( addrw === "h133".U ){
      syncPoint := Cat( syncPoint(63,32), dataw, syncPoint(23,0) ) 
    } .elsewhen( addrw === "h134".U ){
      syncPoint := Cat( syncPoint(63,40), dataw, syncPoint(31,0) ) 
    } .elsewhen( addrw === "h135".U ){
      syncPoint := Cat( syncPoint(63,48), dataw, syncPoint(39,0) ) 
    } .elsewhen( addrw === "h136".U ){
      syncPoint := Cat( syncPoint(63,56), dataw, syncPoint(47,0) ) 
    } .elsewhen( addrw === "h137".U ){
      syncPoint := Cat( dataw, syncPoint(55,0) ) 
    }

    .elsewhen( addrw === "h138".U ){
      syncPeroid := Cat( syncPeroid(31,8), dataw ) 
    } .elsewhen( addrw === "h139".U ){
      syncPeroid := Cat( syncPeroid(31,16), dataw, syncPeroid(7,0) ) 
    } .elsewhen( addrw === "h13a".U ){
      syncPeroid := Cat( syncPeroid(31,24), dataw, syncPeroid(15,0) ) 
    } .elsewhen( addrw === "h13b".U ){
      syncPeroid := Cat( dataw, syncPeroid(23,0) ) 
    }

    for( i <- 1 until 4 ){
      when( addrw === ("h13c".U + (4*(i-1)).U) ){
        syncOffset(i) := Cat( syncOffset(i)(31,8), dataw ) 
      } .elsewhen( addrw === ("h13d".U + (4*(i-1)).U) ){
        syncOffset(i) := Cat( syncOffset(i)(31,16), dataw, syncOffset(i)(7,0) ) 
      } .elsewhen( addrw === ("h13e".U + (4*(i-1)).U) ){
        syncOffset(i) := Cat( syncOffset(i)(31,24), dataw, syncOffset(i)(15,0) ) 
      } .elsewhen( addrw === ("h13f".U + (4*(i-1)).U) ){
        syncOffset(i) := Cat( dataw, syncOffset(i)(23,0) ) 
      }      
    }
  }



}

trait InterfaceCheckSM{ this: InterfaceBase =>
  val isEnW: Bool
  val addrw: UInt
  val dataw: UInt
  val isEnR: Bool


  val smTrigLen_H = for( i <- 0 until 8 ) yield { RegInit(0.U(8.W)) }
  val smTrigLen_L = for( i <- 0 until 8 ) yield { RegInit(0.U(8.W)) }


  for( i <- 0 until 8 ){
    cReg.smTrigLen(i) := Cat( smTrigLen_H(i), smTrigLen_L(i) )

    when( isEnW & addrw === ("h303".U + (i*4).U) ){
      smTrigLen_H(i) := dataw
    } .elsewhen( io.lvds.isEnW & io.lvds.addrw === ("h303".U + (i*4).U)){
      smTrigLen_H(i) := io.lvds.dataw
    }

    when( isEnW & addrw === ("h302".U + (i*4).U) ){
      smTrigLen_L(i) := dataw
    } .elsewhen( io.lvds.isEnW & io.lvds.addrw === ("h302".U + (i*4).U)){
      smTrigLen_L(i) := io.lvds.dataw
    }


      // Cat(
      //   RegEnable( dataw, 0.U, isEnW & addrw === ("h303".U + (i*4).U) ),
      //   RegEnable( dataw, 0.U, isEnW & addrw === ("h302".U + (i*4).U) ),
      // )

  }


  io.sram_r(0).addrr := addrr
  io.sram_r(1).addrr := addrr
  io.sram_r(2).addrr := addrr
  io.sram_r(3).addrr := addrr

  io.sram_r(0).enr   := isEnR & (( addrr & "hF800".U ) === "h0800".U)
  io.sram_r(1).enr   := isEnR & (( addrr & "hF800".U ) === "h1800".U)
  io.sram_r(2).enr   := isEnR & (( addrr & "hF800".U ) === "h2800".U)
  io.sram_r(3).enr   := isEnR & (( addrr & "hF800".U ) === "h3800".U)

  io.sram_w(0).addrw := addrw
  io.sram_w(1).addrw := addrw
  io.sram_w(2).addrw := addrw
  io.sram_w(3).addrw := addrw

  io.sram_w(0).dataw := dataw
  io.sram_w(1).dataw := dataw
  io.sram_w(2).dataw := dataw
  io.sram_w(3).dataw := dataw

  io.sram_w(0).enw   := isEnW & (( addrw & "hF800".U ) === "h1000".U)
  io.sram_w(1).enw   := isEnW & (( addrw & "hF800".U ) === "h2000".U)
  io.sram_w(2).enw   := isEnW & (( addrw & "hF800".U ) === "h3000".U)
  io.sram_w(3).enw   := isEnW & (( addrw & "hF800".U ) === "h4000".U)

  io.dSMdeq(0) := isEnR & (( addrr & "hF800".U ) === "h0800".U) & (addrr(10,0) === cReg.smTrigLen(0) - 1.U + 1.U)
  io.dSMdeq(1) := isEnR & (( addrr & "hF800".U ) === "h1800".U) & (addrr(10,0) === cReg.smTrigLen(2) - 1.U + 1.U)
  io.dSMdeq(2) := isEnR & (( addrr & "hF800".U ) === "h2800".U) & (addrr(10,0) === cReg.smTrigLen(4) - 1.U + 1.U)
  io.dSMdeq(3) := isEnR & (( addrr & "hF800".U ) === "h3800".U) & (addrr(10,0) === cReg.smTrigLen(6) - 1.U + 1.U)

  io.uSMenq(0) := isEnW & (( addrw & "hF800".U ) === "h1000".U) & (addrw(10,0) === cReg.smTrigLen(1) - 1.U)
  io.uSMenq(1) := isEnW & (( addrw & "hF800".U ) === "h2000".U) & (addrw(10,0) === cReg.smTrigLen(3) - 1.U)
  io.uSMenq(2) := isEnW & (( addrw & "hF800".U ) === "h3000".U) & (addrw(10,0) === cReg.smTrigLen(5) - 1.U)
  io.uSMenq(3) := isEnW & (( addrw & "hF800".U ) === "h4000".U) & (addrw(10,0) === cReg.smTrigLen(7) - 1.U)
}

trait InterfaceLVDSop{ this: InterfaceBase =>
  
  io.lvds.datar := RegEnable(AcquireReg(addr = io.lvds.addrr), io.lvds.isEnR)

  when( io.lvds.isEnW & isSlvMode ){

    when( io.lvds.addrw === "h120".U ){
      syncCfg := io.lvds.dataw
    }

    for( i <- 0 until 4 ){
      when( io.lvds.addrw === ("h122".U + (2*i).U)){
        syncWidth(i) := Cat( syncWidth(i)(15,8), io.lvds.dataw ) 
      } .elsewhen( io.lvds.addrw === ("h123".U + (2*i).U) ){
        syncWidth(i) := Cat( io.lvds.dataw, syncWidth(i)(7,0) ) 
      }
    }

    .elsewhen( io.lvds.addrw === "h130".U ){
      syncPoint := Cat( syncPoint(63,8), io.lvds.dataw ) 
    } .elsewhen( io.lvds.addrw === "h131".U ){
      syncPoint := Cat( syncPoint(63,16), io.lvds.dataw, syncPoint(7,0) ) 
    } .elsewhen( io.lvds.addrw === "h132".U ){
      syncPoint := Cat( syncPoint(63,24), io.lvds.dataw, syncPoint(15,0) ) 
    } .elsewhen( io.lvds.addrw === "h133".U ){
      syncPoint := Cat( syncPoint(63,32), io.lvds.dataw, syncPoint(23,0) ) 
    } .elsewhen( io.lvds.addrw === "h134".U ){
      syncPoint := Cat( syncPoint(63,40), io.lvds.dataw, syncPoint(31,0) ) 
    } .elsewhen( io.lvds.addrw === "h135".U ){
      syncPoint := Cat( syncPoint(63,48), io.lvds.dataw, syncPoint(39,0) ) 
    } .elsewhen( io.lvds.addrw === "h136".U ){
      syncPoint := Cat( syncPoint(63,56), io.lvds.dataw, syncPoint(47,0) ) 
    } .elsewhen( io.lvds.addrw === "h137".U ){
      syncPoint := Cat( io.lvds.dataw, syncPoint(55,0) ) 
    }

    .elsewhen( io.lvds.addrw === "h138".U ){
      syncPeroid := Cat( syncPeroid(31,8), io.lvds.dataw ) 
    } .elsewhen( io.lvds.addrw === "h139".U ){
      syncPeroid := Cat( syncPeroid(31,16), io.lvds.dataw, syncPeroid(7,0) ) 
    } .elsewhen( io.lvds.addrw === "h13a".U ){
      syncPeroid := Cat( syncPeroid(31,24), io.lvds.dataw, syncPeroid(15,0) ) 
    } .elsewhen( io.lvds.addrw === "h13b".U ){
      syncPeroid := Cat( io.lvds.dataw, syncPeroid(23,0) ) 
    }

    for( i <- 1 until 4 ){
      when( io.lvds.addrw === ("h13c".U + (4*(i-1)).U) ){
        syncOffset(i) := Cat( syncOffset(i)(31,8), io.lvds.dataw ) 
      } .elsewhen( io.lvds.addrw === ("h13d".U + (4*(i-1)).U) ){
        syncOffset(i) := Cat( syncOffset(i)(31,16), io.lvds.dataw, syncOffset(i)(7,0) ) 
      } .elsewhen( io.lvds.addrw === ("h13e".U + (4*(i-1)).U) ){
        syncOffset(i) := Cat( syncOffset(i)(31,24), io.lvds.dataw, syncOffset(i)(15,0) ) 
      } .elsewhen( io.lvds.addrw === ("h13f".U + (4*(i-1)).U) ){
        syncOffset(i) := Cat( io.lvds.dataw, syncOffset(i)(23,0) ) 
      }      
    }
  }
}

trait InterfaceSync{ this: InterfaceBase =>
  cReg.timeStamp := RegNext( cReg.timeStamp + 1.U, 0.U )

  cReg.mstDeltaTime := io.mstDeltaTime


  // sReg.mstTimeStamp := io.mstTimeStamp
  sReg.deltaFinal := io.deltaFinal
  sReg.recoTimeStamp := RegNext( cReg.timeStamp + Cat( Fill(32, sReg.deltaFinal.extract(31)), sReg.deltaFinal ) )
  sReg.slvDeltaTime := io.slvDeltaTime
  
  val syncSign = for( i <- 0 until 4 ) yield { RegInit(false.B) }
  val syncOffsetCnt = for( i <- 0 until 4 ) yield { RegInit("hFFFFFFFF".U(32.W)) } //空开第0位
  val syncResetCnt = for( i <- 0 until 4 ) yield { RegInit(0.U(16.W)) } //空开第0位


  when( cReg.syncPoint === sReg.recoTimeStamp ){ //时间到达sync0时间点
    syncSign(0) := true.B
    syncPoint := syncPoint + cReg.syncPeroid
  } .elsewhen( ~sReg.syncCfg(4+0) & syncResetCnt(0) === sReg.syncWidth(0) ){
    syncSign(0) := false.B
  } .elsewhen( sReg.syncCfg(4+0) & isEnW & addrw === "h122".U ){
    syncSign(0) := false.B
  }

  for( i <- 1 until 4 ) {

    when( cReg.syncPoint === sReg.recoTimeStamp ){ //时间到达sync0时间点
      syncOffsetCnt(i) := 0.U
    } .elsewhen( syncOffsetCnt(i) <= sReg.syncOffset(i) ){
      syncOffsetCnt(i) := syncOffsetCnt(i) + 1.U
    }

    when( syncOffsetCnt(i) === sReg.syncOffset(i) ){
      syncSign(i) := true.B
    } .elsewhen( ~sReg.syncCfg(4+i) & syncResetCnt(i) === sReg.syncWidth(i) ){
      syncSign(i) := false.B
    } .elsewhen( sReg.syncCfg(4+i) & isEnW & addrw === ("h122".U + (2*i).U) ){
      syncSign(i) := false.B
    }

  }

  for( i <- 0 until 4 ){
    when( ~sReg.syncCfg(4+i) ){
      when( syncSign(i) ){
        syncResetCnt(i) := syncResetCnt(i) + 1.U
      } .otherwise{
        syncResetCnt(i) := 0.U
      }
    }

  }




  io.sync(0) := sReg.syncCfg.extract(0) & syncSign(0) & isSlvMode
  io.sync(1) := sReg.syncCfg.extract(1) & syncSign(1) & isSlvMode
  io.sync(2) := sReg.syncCfg.extract(2) & syncSign(2) & isSlvMode
  io.sync(3) := sReg.syncCfg.extract(3) & syncSign(3) & isSlvMode

}

trait InterfaceSystem{ this: InterfaceBase =>
  io.isSoftReset := ShiftRegister( isEnW & addrw === "h40".U, 16, false.B, true.B )
}

class Interface extends InterfaceBase
with InterfaceMCUop
with InterfaceCheckSM
with InterfaceLVDSop
with InterfaceSync
with InterfaceSystem
{


  io.txReq.bits.txSM  := mReg.txSM
  io.txReq.bits.rxSM  := mReg.rxSM
  // io.txReq.bits.txLength := //mReg.txLength
  io.txReq.valid := isEnW & addrw === "h20".U & dataw.extract(0) === "b1".U //& mReg.txLength =/= 0.U




  sReg.localDevIndex := io.localDevIndex

  // sReg.isDevOnLeft        := io.isDevOnLeft
  // sReg.isDevOnLeftModify  := io.isDevOnLeftModify
  // sReg.indexOfLeftDev     := io.indexOfLeftDev
  sReg.isDevOnRight       := io.isDevOnRight
  sReg.isDevOnRightModify := io.isDevOnRightModify
  sReg.indexOfRightDev    := io.indexOfRightDev

  io.initEncryptor.valid := dataw.extract(0) & isEnW & addrw === "h60".U & cReg.mstOrSlv === 0.U //cReg.isEncrypt
  io.initEncryptor.bits  := cReg.encryptKey


}