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硬件中断使能时钟为高

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This commit is contained in:
Ruige Lee
2025-08-06 11:42:59 +08:00
parent fc4fe95ffe
commit fd3bae6a04
1 changed files with 4 additions and 2 deletions
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6
src/main/scala/backBoard/shin/Interface.scala
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@@ -953,8 +953,10 @@ trait InterfaceSystem{ this: InterfaceBase =>
cReg.intEnable :=
Cat(
1.U(1.W), //复位中断，时钟为1
RegEnable( dataw(6,0), 0.U, isEnW & addrw === "h73".U ),
1.U(1.W), //复位中断，时钟为1 //31 上电复位
1.U(1.W), //复位中断，时钟为1 //30 上行硬件错误
1.U(1.W), //复位中断，时钟为1 //29 下行硬件错误
RegEnable( dataw(4,0), 0.U, isEnW & addrw === "h73".U ),
RegEnable( dataw, 0.U, isEnW & addrw === "h72".U ),
RegEnable( dataw, 0.U, isEnW & addrw === "h71".U ),
RegEnable( dataw, 0.U, isEnW & addrw === "h70".U ),