From fd3bae6a04a00ad3c32c0bec27ef0a61b312231e Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Wed, 6 Aug 2025 11:42:59 +0800 Subject: [PATCH] =?UTF-8?q?=E7=A1=AC=E4=BB=B6=E4=B8=AD=E6=96=AD=E4=BD=BF?= =?UTF-8?q?=E8=83=BD=E6=97=B6=E9=92=9F=E4=B8=BA=E9=AB=98?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/Interface.scala | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala index bb70219..bd31d84 100644 --- a/src/main/scala/backBoard/shin/Interface.scala +++ b/src/main/scala/backBoard/shin/Interface.scala @@ -953,8 +953,10 @@ trait InterfaceSystem{ this: InterfaceBase => cReg.intEnable := Cat( - 1.U(1.W), //复位中断，时钟为1 - RegEnable( dataw(6,0), 0.U, isEnW & addrw === "h73".U ), + 1.U(1.W), //复位中断，时钟为1 //31 上电复位 + 1.U(1.W), //复位中断，时钟为1 //30 上行硬件错误 + 1.U(1.W), //复位中断，时钟为1 //29 下行硬件错误 + RegEnable( dataw(4,0), 0.U, isEnW & addrw === "h73".U ), RegEnable( dataw, 0.U, isEnW & addrw === "h72".U ), RegEnable( dataw, 0.U, isEnW & addrw === "h71".U ), RegEnable( dataw, 0.U, isEnW & addrw === "h70".U ),