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增加复位code特性

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This commit is contained in:
Ruige Lee
2025-08-01 11:15:24 +08:00
parent 73dbf4d05a
commit d5a52a651b
1 changed files with 17 additions and 10 deletions
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27
src/main/scala/backBoard/shin/Interface.scala
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@@ -42,21 +42,13 @@ class CommonRegisterBundle extends Bundle{
val spiSel = UInt(2.W)
val softResetCode = Vec(4, UInt(8.W))
val intEnable = UInt(32.W)
val intStatus = UInt(32.W)
val intMode = UInt(16.W)
// val upRecErrorCnt = UInt(32.W)
// val downRecErrorCnt = UInt(32.W)
// val upForwardErrorCnt = UInt(32.W)
// val downForwardErrorCnt = UInt(32.W)
// val qspiErrorCnt = UInt(32.W)
// val forwardCnt = UInt(32.W)
// val recByteCnt = UInt(32.W)
// val forwardByteCnt = UInt(32.W)
val statDownRecErrorCnt = UInt(32.W)
val statDownRecHeaderErrorCnt = UInt(16.W)
@@ -271,6 +263,11 @@ abstract class InterfaceBase extends Module{
Seq(
(addr === "h40".U ) -> cReg.softResetCode(1),
(addr === "h41".U ) -> cReg.softResetCode(1),
(addr === "h42".U ) -> cReg.softResetCode(2),
(addr === "h43".U ) -> cReg.softResetCode(3),
(addr === "h70".U ) -> cReg.intEnable(7,0),
(addr === "h71".U ) -> cReg.intEnable(15,8),
(addr === "h72".U ) -> cReg.intEnable(23,16),
@@ -941,7 +938,17 @@ trait InterfaceSync{ this: InterfaceBase =>
// }
trait InterfaceSystem{ this: InterfaceBase =>
io.isSoftReset := ShiftRegister( isEnW & addrw === "h40".U, 16, false.B, true.B )
io.isSoftReset :=
cReg.softResetCode(0) === "h01".U &
cReg.softResetCode(1) === "h00".U &
cReg.softResetCode(2) === "h66".U &
cReg.softResetCode(3) === "h79".U
cReg.softResetCode(0) := RegEnable(dataw, 0.U, isEnW & addrw === "h40".U )
cReg.softResetCode(1) := RegEnable(dataw, 0.U, isEnW & addrw === "h41".U )
cReg.softResetCode(2) := RegEnable(dataw, 0.U, isEnW & addrw === "h42".U )
cReg.softResetCode(3) := RegEnable(dataw, 0.U, isEnW & addrw === "h43".U )
cReg.intEnable :=
Cat(