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ebmmu提升到16个

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This commit is contained in:
Ruige Lee
2025-08-06 17:44:16 +08:00
parent 1eb19cbca7
commit 73e1061c0b
2 changed files with 9 additions and 9 deletions
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6
src/main/scala/backBoard/shin/Interface.scala
View File

@@ -114,7 +114,7 @@ class MasterRegisterBundle extends Bundle{
class SlaveRegisterBundle extends Bundle{
val ebmmu = Vec(8, new EBMMU_Bundle)
val ebmmu = Vec(16, new EBMMU_Bundle)
val localDevIndex = UInt(16.W)
@@ -439,7 +439,7 @@ abstract class InterfaceBase extends Module{
( 0 until 128 ).map{ i =>
( addr === ("h180".U(16.W) + i.U ) ) -> cReg.custom(i)
} ++
( 0 until 8 ).map{ i => Seq(
( 0 until 16 ).map{ i => Seq(
( ( addr === ( "h200".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).lAddr( 7, 0),
( ( addr === ( "h201".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).lAddr(15, 8),
( ( addr === ( "h202".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).lAddr(23,16),
@@ -702,7 +702,7 @@ trait InterfaceLVDSop{ this: InterfaceBase =>
io.lvds.datar := RegEnable(AcquireReg(addr = io.lvds.addrr), io.lvds.isEnR)
( 0 until 8 ).map{ i =>
( 0 until 16 ).map{ i =>
sReg.ebmmu(i).lAddr := Cat(
RegEnable( io.lvds.dataw(5,0), 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h203".U(16.W) + (10*i).U )) ),
RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h202".U(16.W) + (10*i).U )) ),

12
src/main/scala/backBoard/shin/SlaveParser.scala
View File

@@ -506,19 +506,19 @@ trait SlaveParserRW{ this: SlaveParserBase =>
val isDownLgcAddrwAcquireTrans = //是否触发地址转换
(downTransLenCnt === 0.U) & ( (0 until 8).map{ i =>
(downTransLenCnt === 0.U) & ( (0 until 16).map{ i =>
sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_WR || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrwNext === sReg.ebmmu(i).lAddr)
}.reduce(_|_))
val acquireDownPhyAddrw = Mux1H( //选择一个ebmmu
(0 until 8).map{ i =>
(0 until 16).map{ i =>
(sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_WR || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrwNext === sReg.ebmmu(i).lAddr)) ->
sReg.ebmmu(i).pAddr
}
)
val acquireDownTransLen = Mux1H( //选择一个ebmmu
(0 until 8).map{ i =>
(0 until 16).map{ i =>
(sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_WR || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrwNext === sReg.ebmmu(i).lAddr)) ->
sReg.ebmmu(i).length
}
@@ -631,19 +631,19 @@ trait SlaveParserRW{ this: SlaveParserBase =>
val isUpLgcAddrrAcquireTrans = //是否触发地址转换
(upTransLenCnt === 0.U) & ( (0 until 8).map{ i =>
(upTransLenCnt === 0.U) & ( (0 until 16).map{ i =>
sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_RD || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrrNext === sReg.ebmmu(i).lAddr)
}.reduce(_|_))
val acquireUpPhyAddrr = Mux1H( //选择一个ebmmu
(0 until 8).map{ i =>
(0 until 16).map{ i =>
(sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_RD || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrrNext === sReg.ebmmu(i).lAddr)) ->
sReg.ebmmu(i).pAddr
}
)
val acquireUpTransLen = Mux1H( //选择一个ebmmu
(0 until 8).map{ i =>
(0 until 16).map{ i =>
(sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_RD || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrrNext === sReg.ebmmu(i).lAddr)) ->
sReg.ebmmu(i).length
}