From 73e1061c0bb4d86a90e0a0374f4309e5c57e40fa Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Wed, 6 Aug 2025 17:44:16 +0800 Subject: [PATCH] =?UTF-8?q?ebmmu=E6=8F=90=E5=8D=87=E5=88=B016=E4=B8=AA?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/Interface.scala | 6 +++--- src/main/scala/backBoard/shin/SlaveParser.scala | 12 ++++++------ 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala index 0626e48..13b195b 100644 --- a/src/main/scala/backBoard/shin/Interface.scala +++ b/src/main/scala/backBoard/shin/Interface.scala @@ -114,7 +114,7 @@ class MasterRegisterBundle extends Bundle{ class SlaveRegisterBundle extends Bundle{ - val ebmmu = Vec(8, new EBMMU_Bundle) + val ebmmu = Vec(16, new EBMMU_Bundle) val localDevIndex = UInt(16.W) @@ -439,7 +439,7 @@ abstract class InterfaceBase extends Module{ ( 0 until 128 ).map{ i => ( addr === ("h180".U(16.W) + i.U ) ) -> cReg.custom(i) } ++ - ( 0 until 8 ).map{ i => Seq( + ( 0 until 16 ).map{ i => Seq( ( ( addr === ( "h200".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).lAddr( 7, 0), ( ( addr === ( "h201".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).lAddr(15, 8), ( ( addr === ( "h202".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).lAddr(23,16), @@ -702,7 +702,7 @@ trait InterfaceLVDSop{ this: InterfaceBase => io.lvds.datar := RegEnable(AcquireReg(addr = io.lvds.addrr), io.lvds.isEnR) - ( 0 until 8 ).map{ i => + ( 0 until 16 ).map{ i => sReg.ebmmu(i).lAddr := Cat( RegEnable( io.lvds.dataw(5,0), 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h203".U(16.W) + (10*i).U )) ), RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h202".U(16.W) + (10*i).U )) ), diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala index e8cc1c6..8b2081b 100644 --- a/src/main/scala/backBoard/shin/SlaveParser.scala +++ b/src/main/scala/backBoard/shin/SlaveParser.scala @@ -506,19 +506,19 @@ trait SlaveParserRW{ this: SlaveParserBase => val isDownLgcAddrwAcquireTrans = //是否触发地址转换 - (downTransLenCnt === 0.U) & ( (0 until 8).map{ i => + (downTransLenCnt === 0.U) & ( (0 until 16).map{ i => sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_WR || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrwNext === sReg.ebmmu(i).lAddr) }.reduce(_|_)) val acquireDownPhyAddrw = Mux1H( //选择一个ebmmu - (0 until 8).map{ i => + (0 until 16).map{ i => (sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_WR || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrwNext === sReg.ebmmu(i).lAddr)) -> sReg.ebmmu(i).pAddr } ) val acquireDownTransLen = Mux1H( //选择一个ebmmu - (0 until 8).map{ i => + (0 until 16).map{ i => (sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_WR || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrwNext === sReg.ebmmu(i).lAddr)) -> sReg.ebmmu(i).length } @@ -631,19 +631,19 @@ trait SlaveParserRW{ this: SlaveParserBase => val isUpLgcAddrrAcquireTrans = //是否触发地址转换 - (upTransLenCnt === 0.U) & ( (0 until 8).map{ i => + (upTransLenCnt === 0.U) & ( (0 until 16).map{ i => sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_RD || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrrNext === sReg.ebmmu(i).lAddr) }.reduce(_|_)) val acquireUpPhyAddrr = Mux1H( //选择一个ebmmu - (0 until 8).map{ i => + (0 until 16).map{ i => (sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_RD || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrrNext === sReg.ebmmu(i).lAddr)) -> sReg.ebmmu(i).pAddr } ) val acquireUpTransLen = Mux1H( //选择一个ebmmu - (0 until 8).map{ i => + (0 until 16).map{ i => (sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_RD || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrrNext === sReg.ebmmu(i).lAddr)) -> sReg.ebmmu(i).length }