eb001/src/main/scala/backBoard/LocalRegisters.scala

package BACK

import chisel3._
import chisel3.util._

class ManualParamBundle extends Bundle{
  val vendorID = UInt( 16.W )
  val moduleID = UInt( 16.W )
  val hwVersion = UInt( 16.W )
  val swVersion = UInt( 16.W )
  // val batchID  = UInt( 16.W )
  val serial   = UInt( 48.W )
}


abstract class BackBoardSlvLocal extends BackBoardSlvBase with BackBoardSlvDown with BackBoardSlvUp{

  val param = IO(Input( new ManualParamBundle ))

  val statusPage = RegEnable( downRegTemp(0)(3,0), 15.U, isCrcPass )
  val statusP    = RegInit(false.B)
  val statusRF   = RegInit(false.B)
  val statusPR   = RegEnable( Cat( downRegTemp(1).extract(0), downRegTemp(0).extract(7) ), 0.U, isCrcPass )
  val statusER   = RegInit(false.B)
  val statusLE   = RegInit(false.B)
  val statusSync = RegEnable( downRegTemp(1).extract(3).asBool, false.B, isCrcPass )
  val statusNone = ~io.isLast



  upReg(0) := Cat( statusPR.extract(0), statusRF, statusP, 0.U(1.W), statusPage )
  upReg(1) := Cat( statusNone, statusSync, statusLE, statusER, statusPR.extract(1) )

  when( statusPage === 15.U ){
    upReg(2) := 0.U
    upReg(3) := 0.U

    upReg(4) := 0.U
    upReg(5) := 0.U

    upReg(6) := param.vendorID(7,0)
    upReg(7) := param.vendorID(15,8)

    upReg(8) := param.moduleID(7,0)
    upReg(9) := param.moduleID(15,8)

    upReg(10) := param.hwVersion(7,0)
    upReg(11) := param.hwVersion(15,8)

    upReg(12) := param.swVersion(7,0)
    upReg(13) := param.swVersion(15,8)

    // upReg(15) := param.batchID(7,0)
    // upReg(16) := param.batchID(15,8)

    upReg(14) := param.serial(7,0)
    upReg(15) := param.serial(15,8)
    upReg(16) := param.serial(23,16)
    upReg(17) := param.serial(31,24)
    upReg(18) := param.serial(39,32)
    upReg(19) := param.serial(47,40)    
  }



  val (usCounter, usTrigger) = Counter(Range(0, 10))

  io.isOnline := false.B

  val isUpdate = (statusSync & ~RegNext(io.DCIn) & io.DCIn) | (~statusSync)

}





trait BackBoardSlvStatusPR { this: BackBoardSlvLocal =>
  val flashCounter = RegInit( 0.U( 19.W ) )
  val flash2HZ = Reg(Bool())
  val flash1HZ = Reg(Bool())


  when( usTrigger ){
    when( flashCounter >= 500000.U ){
      flashCounter := 0.U
      flash2HZ := ~flash2HZ
      when( flash2HZ ){
        flash1HZ := ~flash1HZ
      }
    } .otherwise{
      flashCounter := flashCounter + 1.U      
    }
  }



  val LED_PR = IO(Output( Bool() ))

  LED_PR := ~Mux( statusPR === "b00".U, flash2HZ,
              Mux( statusPR === "b01".U, flash1HZ, 
                Mux( statusPR === "b10".U, true.B, false.B
                  )))
}



trait BackBoardSlvIn16 { this: BackBoardSlvLocal =>

  val inPin = Wire(UInt(16.W))


  val flitCnt = RegInit(MixedVecInit(Seq( false.B, 0.U(4.W), false.B, false.B, false.B, false.B, false.B, false.B, false.B) ))
  val flitTrigger = Wire(Vec(9, Bool()))
  val digitalFilter = for( i <- 0 until 2 ) yield { RegInit( 1.U(8.W) ) }
  val digitalIn     = for( i <- 0 until 2 ) yield { Reg( Vec(8, Bool()) ) }


  flitTrigger(0) := ~RegNext(flitTrigger(0))

  flitTrigger(1) := flitCnt(1) === 15.U
  when( ~RegNext(usTrigger) & usTrigger ){
    flitCnt(1) := flitCnt(1) + 1.U      
  }

  flitTrigger(2) := flitCnt(2)
  when( ~RegNext(flitTrigger(1)) & flitTrigger(1) ){
    flitCnt(2) := ~flitCnt(2)
  }

  flitTrigger(3) := flitCnt(3)
  when( ~RegNext(flitTrigger(2)) & flitTrigger(2) ){
    flitCnt(3) := ~flitCnt(3)
  }

  flitTrigger(4) := flitCnt(4)
  when( ~RegNext(flitTrigger(3)) & flitTrigger(3) ){
    flitCnt(4) := ~flitCnt(4)
  }

  flitTrigger(5) := flitCnt(5)
  when( ~RegNext(flitTrigger(4)) & flitTrigger(4) ){
    flitCnt(5) := ~flitCnt(5)
  }

  flitTrigger(6) := flitCnt(6)
  when( ~RegNext(flitTrigger(5)) & flitTrigger(5) ){
    flitCnt(6) := ~flitCnt(6)
  }

  flitTrigger(7) := flitCnt(7)
  when( ~RegNext(flitTrigger(6)) & flitTrigger(6) ){
    flitCnt(7) := ~flitCnt(7)
  }

  flitTrigger(8) := flitCnt(8)
  when( ~RegNext(flitTrigger(7)) & flitTrigger(7) ){
    flitCnt(8) := ~flitCnt(8)
  }






  for( i <- 0 until 8 ) {
    for( j <- 0 until 2 ) {
      val flitter = RegInit(VecInit( Seq.fill(16){false.B}))
      val flitHi  = RegInit(0.U((log2Ceil(16)).W))
      val shiftIn = RegNext( inPin(i+8*j) )

      val sample = 
        Mux( digitalFilter(j) === 1.U, ~RegNext(flitTrigger(1)) & flitTrigger(1),
          Mux(digitalFilter(j) === 2.U, ~RegNext(flitTrigger(2)) & flitTrigger(2),
            Mux(digitalFilter(j) === 3.U, ~RegNext(flitTrigger(3)) & flitTrigger(3),
              Mux(digitalFilter(j) === 4.U, ~RegNext(flitTrigger(4)) & flitTrigger(4),
                Mux(digitalFilter(j) === 5.U, ~RegNext(flitTrigger(5)) & flitTrigger(5),
                  Mux(digitalFilter(j) === 6.U, ~RegNext(flitTrigger(6)) & flitTrigger(6),
                    Mux(digitalFilter(j) === 7.U, ~RegNext(flitTrigger(7)) & flitTrigger(7),
                      Mux(digitalFilter(j) === 8.U, ~RegNext(flitTrigger(8)) & flitTrigger(8), true.B
                      ))))))))


      when( sample ){
        flitter(0) := shiftIn
        (1 until 16).map{ k =>
          flitter(k) := flitter(k-1)
        }

        when( ~flitter(15) & flitter(0) ){
          flitHi := flitHi + 1.U
        } .elsewhen( flitter(15) & ~flitter(0) ){
          flitHi := flitHi - 1.U
        }

        when( flitHi === 12.U ){
          digitalIn(j)(i) := true.B
        } .elsewhen( flitHi === 3.U ){
          digitalIn(j)(i) := false.B
        }      

        // val fliterCnt = WireDefault( VecInit( (1 until 16).map{ k => flitter(k) }) )

        // assert( flitHi <= 15.U )
        // assert( fliterCnt.count( (k:Bool) => k === true.B ) === flitHi )

      }
    }
  }

}




class DIn16 extends BackBoardSlvLocal
with BackBoardSlvStatusPR
with BackBoardSlvIn16{
  
  val in = IO(Input(UInt(16.W)))

  inPin := in


  when( isCrcPass & downRegTemp(0)(3,0) === 0.U ){
    digitalFilter(0) := downRegTemp(4)
    digitalFilter(1) := downRegTemp(5)
  }

  val digitalInSync = for( i <- 0 until 2 ) yield { RegEnable( Cat( digitalIn(i).reverse ), isUpdate ) }

  when( statusPage === 0.U ){
    upReg(2) := digitalInSync(0)
    upReg(3) := digitalInSync(1)
    upReg(4) := digitalFilter(0)
    upReg(5) := digitalFilter(1)
  }
}




trait BackBoardSlvOut16{ this: BackBoardSlvLocal =>

  val outRegSync  = Wire(UInt(16.W))

  val mthodReg = RegInit(0.U(16.W))
  val valueReg = RegInit(0.U(16.W))

  val outPin = Wire(UInt(16.W))

  outPin := 
    Mux(statusPR === 3.U, outRegSync, (mthodReg & valueReg) | (~mthodReg & outRegSync))

}


class DOut16 extends BackBoardSlvLocal
with BackBoardSlvStatusPR
with BackBoardSlvOut16{
  val out = IO(Output(UInt(16.W)))
  val flt = IO(Input(Vec(2, Bool())))
  val outReg  = RegInit(0.U(16.W))

  when( isCrcPass & downRegTemp(0)(3,0) === 0.U ){
    outReg := Cat(downRegTemp(3), downRegTemp(2))
  }
  when( isCrcPass & downRegTemp(0)(3,0) === 1.U & downRegTemp(2).extract(0) ){
    mthodReg := Cat(downRegTemp(3), downRegTemp(2))
    valueReg := Cat(downRegTemp(5), downRegTemp(4))
  }

  outRegSync := RegEnable( outReg, 0.U, isUpdate )

  when( statusPage === 0.U ){
    upReg(2) := outReg(7,0)
    upReg(3) := outReg(15,8)
    upReg(4) := Cat( ~flt(1), ~flt(0) )
  }

  when( statusPage === 1.U ){
    upReg(2) := RegEnable(downRegTemp(2).extract(0), isCrcPass & downRegTemp(0)(3,0) === 1.U)

    upReg(4) := mthodReg(7,0)
    upReg(5) := mthodReg(15,8)
    upReg(6) := valueReg(7,0)
    upReg(7) := valueReg(15,8)
  }

  // out := outPin

  val isDownCDR = RegInit(false.B)
  val isUpCDR   = RegInit(false.B)

  when( isCrcPass ){
    isDownCDR := false.B
    isUpCDR   := false.B
  } .elsewhen( io.lvdsSlv.downstream_rx_cdr_err ){
    isDownCDR := true.B
  } .elsewhen(io. lvdsSlv.upstream_rx_cdr_err ){
    isUpCDR   := true.B
  }

  //override
  out := Mux( isDownCDR & isUpCDR, "h5555".U, Mux(isDownCDR, Cat(Fill(16, flash1HZ)), Mux( isUpCDR, Cat(Fill(16, flash2HZ)), outPin )))


}