eb001/src/main/scala/backBoard/LocalRegisters.scala

package BACK

import chisel3._
import chisel3.util._

class ManualParamBundle extends Bundle{
  val vendorID = UInt( 16.W )
  val moduleID = UInt( 16.W )
  val hwVersion = UInt( 16.W )
  val swVersion = UInt( 16.W )
  val batchID  = UInt( 16.W )
  val serial   = UInt( 48.W )
}


abstract class BackBoardSlvLocal extends BackBoardSlvBase with BackBoardSlvDown with BackBoardSlvUp{

  // def STATUSWR_ADDR     : UInt = "h00".U //01
  // def DATA_PERWR_ADDR   : UInt = "h02".U //03
  // def DATA_SINWR_ADDR   : UInt = "h04".U //05


  // def STATUSRD_ADDR     : UInt = "h00".U //01
  // def DATA_PERRD_ADDR   : UInt = "h02".U //03
  // def DATA_SINRD_ADDR   : UInt = "h04".U //05



  // def VENDORID_ADDR     : UInt = "h10".U
  // def MODULEID_ADDR     : UInt = "h12".U
  // def HVERSION_ADDR     : UInt = "h14".U
  // def SVERSION_ADDR     : UInt = "h16".U
  // def BATCHNUM_ADDR     : UInt = "h18".U
  // def SERIAL0_ADDR      : UInt = "h1a".U
  // def SERIAL1_ADDR      : UInt = "h1c".U
  // def SERIAL2_ADDR      : UInt = "h1e".U

  val param = IO(Input( new ManualParamBundle ))

  val statusPage = downReg(0)(3,0)
  val statusP    = RegInit(false.B)
  val statusRF   = RegInit(false.B)
  val statusPR   = Cat( downReg(1).extract(0), downReg(0).extract(7) )
  val statusER   = RegInit(false.B)
  val statusLE   = RegInit(false.B)



  upReg(0) := Cat( statusPR.extract(0), statusRF, statusP, 0.U(1.W), statusPage )
  upReg(1) := Cat( statusLE, statusER, statusPR.extract(1) )

  when( statusPage === 15.U ){
    upReg(2) := downReg(2)
    upReg(3) := downReg(3)

    upReg(4) := downReg(4)
    upReg(5) := downReg(5)

    upReg(16) := param.vendorID(7,0)
    upReg(17) := param.vendorID(15,8)

    upReg(18) := param.moduleID(7,0)
    upReg(19) := param.moduleID(15,8)

    upReg(20) := param.hwVersion(7,0)
    upReg(21) := param.hwVersion(15,8)

    upReg(22) := param.swVersion(7,0)
    upReg(23) := param.swVersion(15,8)

    upReg(24) := param.batchID(7,0)
    upReg(25) := param.batchID(15,8)

    upReg(26) := param.serial(7,0)
    upReg(27) := param.serial(15,8)
    upReg(28) := param.serial(23,16)
    upReg(29) := param.serial(31,24)
    upReg(30) := param.serial(39,32)
    upReg(31) := param.serial(47,40)    
  }



  val (usCounter, usTrigger) = Counter(Range(0, 10))


}





trait BackBoardSlvStatusPR { this: BackBoardSlvLocal =>
  val flashCounter = RegInit( 0.U( 19.W ) )
  val flash2HZ = Reg(Bool())
  val flash1HZ = Reg(Bool())


  when( usTrigger ){
    when( flashCounter >= 500000.U ){
      flashCounter := 0.U
      flash2HZ := ~flash2HZ
      when( flash2HZ ){
        flash1HZ := ~flash1HZ
      }
    } .otherwise{
      flashCounter := flashCounter + 1.U      
    }
  }



  val LED_PR = IO(Output( Bool() ))

  LED_PR := ~Mux1H(Seq(
    ( statusPR === "b00".U ) -> flash2HZ,
    ( statusPR === "b01".U ) -> flash1HZ, 
    ( statusPR === "b10".U ) -> true.B,
    ( statusPR === "b11".U ) -> false.B,
    ))
}



trait BackBoardSlvIn { this: BackBoardSlvLocal =>

  def gp: Int


  val in = IO(Input(UInt((8*gp).W)))

  val flitCnt = RegInit(MixedVecInit(Seq( 0.U(1.W), 0.U((log2Ceil(256/32)).W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W)) ))
  val flitTrigger = Wire(Vec(9, Bool()))

  flitTrigger(0) := ~RegNext(flitTrigger(0))

  // flitTrigger(1) := usTrigger

  flitTrigger(1) := flitCnt(1) >= (256/32-1).U
  when( ~RegNext(usTrigger) & usTrigger ){
    when( flitTrigger(1) ){
      flitCnt(1) := 0.U
    } .otherwise{
      flitCnt(1) := flitCnt(1) + 1.U      
    }

  }

  flitTrigger(2) := flitCnt(2) === 1.U
  when( ~RegNext(flitTrigger(1)) & flitTrigger(1) ){
    flitCnt(2) := flitCnt(2) + 1.U
  }

  flitTrigger(3) := flitCnt(3) === 1.U
  when( ~RegNext(flitTrigger(2)) & flitTrigger(2) ){
    flitCnt(3) := flitCnt(3) + 1.U
  }

  flitTrigger(4) := flitCnt(4) === 1.U
  when( ~RegNext(flitTrigger(3)) & flitTrigger(3) ){
    flitCnt(4) := flitCnt(4) + 1.U
  }

  flitTrigger(5) := flitCnt(5) === 1.U
  when( ~RegNext(flitTrigger(4)) & flitTrigger(4) ){
    flitCnt(5) := flitCnt(5) + 1.U
  }

  flitTrigger(6) := flitCnt(6) === 1.U
  when( ~RegNext(flitTrigger(5)) & flitTrigger(5) ){
    flitCnt(6) := flitCnt(6) + 1.U
  }

  flitTrigger(7) := flitCnt(7) === 1.U
  when( ~RegNext(flitTrigger(6)) & flitTrigger(6) ){
    flitCnt(7) := flitCnt(7) + 1.U
  }

  flitTrigger(8) := flitCnt(8) === 1.U
  when( ~RegNext(flitTrigger(7)) & flitTrigger(7) ){
    flitCnt(8) := flitCnt(8) + 1.U
  }

  for( j <- 0 until gp ) {

    val digitalFilter = RegEnable( downReg(4+j), 1.U, statusPage === 0.U )

    val digitalIn = Reg( Vec(8, Bool()) )

    when( statusPage === 0.U ){
      upReg(2+j) := Cat( digitalIn.reverse  )
      upReg(4+j) := downReg(4+j)
    }


    for( i <- 0 until 8 ) {

      val flitter = RegInit(VecInit( Seq.fill(32){false.B}))
      val flitHi  = RegInit(0.U((log2Ceil(32)).W))

      ( 0 until 9 ).map{ k => 
        when( digitalFilter === k.U ){
          when( (if( k == 0 ){ true.B } else {~RegNext(flitTrigger(k)) & flitTrigger(k)}) ){
            flitter(0) := in(i+8*j)
            (1 until 32).map{ k =>
              flitter(k) := flitter(k-1)
            }

            when( (~flitter(31) & ~flitter(0)) | (flitter(31) & flitter(0)) ){
              flitHi := flitHi
            } .elsewhen( ~flitter(31) & flitter(0) ){
              flitHi := flitHi + 1.U
            } .elsewhen( flitter(31) & ~flitter(0) ){
              flitHi := flitHi - 1.U
            }

            when( flitHi >= 26.U ){
              digitalIn(i) := true.B
            } .elsewhen( flitHi <= 6.U ){
              digitalIn(i) := false.B
            }      

            val fliterCnt = WireDefault( VecInit( (1 until 32).map{ k => flitter(k) }) )

            assert( flitHi <= 31.U )
            assert( fliterCnt.count( (k:Bool) => k === true.B ) === flitHi )

          }
        }
      }
    }
  }

}




class DIn16 extends BackBoardSlvLocal
with BackBoardSlvStatusPR
with BackBoardSlvIn{
  def gp = 2

}







// class BackBoardSlvOut16 extends BackBoardSlvLocal{
//   val in  = IO(Input(UInt(32.W)))
//   val out = IO(Output(UInt(32.W)))
//   val oe  = IO(Output(UInt(32.W)))



//   out := Cat( (0 until 4).map{i => downReg(i)}.reverse )
//   oe  := Cat( (4 until 8).map{i => downReg(i)}.reverse )

//   for( i <- 0 until 4 ) {
//     upReg(i) := in( i*8+7,8*i )
//   }
// }