36 lines
730 B
Scala
36 lines
730 B
Scala
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package MAC
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import chisel3._
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import chisel3.util._
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// class LocalRegistersIO extends Bundle{
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// val
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// }
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class LocalRegisters(implicit p: Parameters) extends LazyModule{
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val device = new SimpleDevice("slv",Seq("slv"))
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val configNode = TLRegisterNode(
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address = Seq(AddressSet(0x000L, 0x000000ffL)),
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device = device,
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concurrency = 1,
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beatBytes = 32/8,
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executable = true
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)
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lazy val module = new LocalRegImp(this){
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val digitalDir = RegInit(0.U(32.W))
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configNode.regmap(
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( 0 << 2 ) ->
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RegFieldGroup("DigitalDir", Some("Digital IO Direction"), Seq(
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RegField(32, digitalDir , RegFieldDesc( "digitalDir", "digitalDir", reset = Some(0))) ,
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)),
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)
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}
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}
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