package MAC

import chisel3._
import chisel3.util._

// class LocalRegistersIO extends Bundle{
//   val 
// }



class LocalRegisters(implicit p: Parameters) extends LazyModule{

  val device = new SimpleDevice("slv",Seq("slv"))
  val configNode = TLRegisterNode(
    address = Seq(AddressSet(0x000L, 0x000000ffL)),
    device = device,
    concurrency = 1,
    beatBytes = 32/8,
    executable = true
  )

  lazy val module = new LocalRegImp(this){

    val digitalDir = RegInit(0.U(32.W))


    configNode.regmap(
      ( 0 << 2 ) -> 
        RegFieldGroup("DigitalDir", Some("Digital IO Direction"), Seq(
          RegField(32, digitalDir , RegFieldDesc( "digitalDir", "digitalDir", reset = Some(0))) ,
        )),
    )

  }
}