eb001/src/main/scala/backBoard/LocalRegisters.scala

package BACK

import chisel3._
import chisel3.util._

class ManualParamBundle extends Bundle{
  val vendorID = UInt( 16.W )
  val moduleID = UInt( 16.W )
  val hwVersion = UInt( 16.W )
  val swVersion = UInt( 16.W )
  val batchID  = UInt( 16.W )
  val serial   = UInt( 48.W )
}


abstract class BackBoardSlvLocal extends BackBoardSlvBase with BackBoardSlvDown with BackBoardSlvUp{

  def DATA_SINWR_ADDR   : UInt = "h00".U
  def DATA_PERWR_ADDR   : UInt = "h02".U
  def STATUSWR_ADDR     : UInt = "h04".U

  def DATA_SINRD_ADDR   : UInt = "h00".U
  def DATA_PERRD_ADDR   : UInt = "h02".U
  def STATUSRD_ADDR     : UInt = "h04".U

  def VENDORID_ADDR     : UInt = "h10".U
  def MODULEID_ADDR     : UInt = "h12".U
  def HVERSION_ADDR     : UInt = "h14".U
  def SVERSION_ADDR     : UInt = "h16".U
  def BATCHNUM_ADDR     : UInt = "h18".U
  def SERIAL0_ADDR      : UInt = "h1a".U
  def SERIAL1_ADDR      : UInt = "h1c".U
  def SERIAL2_ADDR      : UInt = "h1e".U

  val param = IO(Input( new ManualParamBundle ))

  val rankNum    = downReg(4)
  val statusLed  = downReg(5)(1,0)

  val (us10Counter, us10Trigger) = Counter(Range(0, 100))

  when( true.B ){


    upReg(16) := param.vendorID(7,0)
    upReg(17) := param.vendorID(15,8)

    upReg(18) := param.moduleID(7,0)
    upReg(19) := param.moduleID(15,8)

    upReg(20) := param.hwVersion(7,0)
    upReg(21) := param.hwVersion(15,8)

    upReg(22) := param.swVersion(7,0)
    upReg(23) := param.swVersion(15,8)

    upReg(24) := param.batchID(7,0)
    upReg(25) := param.batchID(15,8)

    upReg(26) := param.serial(7,0)
    upReg(27) := param.serial(15,8)
    upReg(28) := param.serial(23,16)
    upReg(29) := param.serial(31,24)
    upReg(30) := param.serial(39,32)
    upReg(31) := param.serial(47,40)    
  }


}

trait BackBoardSlvStatusLed { this: BackBoardSlvLocal =>
  val flashCounter = RegInit( 0.U( 16.W ) )
  val flash2HZ = Reg(Bool())
  val flash1HZ = Reg(Bool())


  when( us10Trigger ){
    when( flashCounter >= 50000.U ){
      flashCounter := 0.U
      flash2HZ := ~flash2HZ
      when( flash2HZ ){
        flash1HZ := ~flash1HZ
      }
    } .otherwise{
      flashCounter := flashCounter + 1.U      
    }
  }



  val LED_PR = IO(Output( Bool() ))

  LED_PR := ~Mux1H(Seq(
    ( statusLed === "b00".U ) -> flash2HZ,
    ( statusLed === "b01".U ) -> flash1HZ, 
    ( statusLed === "b10".U ) -> true.B,
    ( statusLed === "b11".U ) -> false.B,
    ))
}



trait BackBoardSlvIn { this: BackBoardSlvLocal =>

  def gp: Int

  val flitCfg = Seq(
    // ( 0.U  -> 0.S ),
    ( 1.U -> (1/2).U), // -> 25.S   
    ( 2.U -> (2/2).U), // -> 50.S   
    ( 3.U -> (4/2).U), // -> 100.S  
    ( 4.U -> (8/2).U), // -> 200.S  
    ( 5.U -> (16/2).U), // -> 400.S  
    ( 6.U -> (32/2).U), // -> 800.S  
    ( 7.U -> (64/2).U), // -> 1600.S 
    ( 8.U -> (128/2).U), // -> 3200.S 
  )

  val in = IO(Input(UInt((8*gp).W)))

  val flitCnt = RegInit(MixedVecInit(Seq( 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W)) ))
  val flitTrigger = Wire(Vec(9, Bool()))

  flitTrigger(0) := true.B

  flitTrigger(1) := us10Trigger
  // when( ~RegNext(us10Trigger) & us10Trigger ){
  //   flitCnt(1) := Mux( flitCnt(1) >= 24.U, 0.U, flitCnt(1) + 1.U )
  // }

  flitTrigger(2) := flitCnt(2) === 1.U
  when( ~RegNext(flitTrigger(1)) & flitTrigger(1) ){
    flitCnt(2) := flitCnt(2) + 1.U
  }

  flitTrigger(3) := flitCnt(3) === 1.U
  when( ~RegNext(flitTrigger(2)) & flitTrigger(2) ){
    flitCnt(3) := flitCnt(3) + 1.U
  }

  flitTrigger(4) := flitCnt(4) === 1.U
  when( ~RegNext(flitTrigger(3)) & flitTrigger(3) ){
    flitCnt(4) := flitCnt(4) + 1.U
  }

  flitTrigger(5) := flitCnt(5) === 1.U
  when( ~RegNext(flitTrigger(4)) & flitTrigger(4) ){
    flitCnt(5) := flitCnt(5) + 1.U
  }

  flitTrigger(6) := flitCnt(6) === 1.U
  when( ~RegNext(flitTrigger(5)) & flitTrigger(5) ){
    flitCnt(6) := flitCnt(6) + 1.U
  }

  flitTrigger(7) := flitCnt(7) === 1.U
  when( ~RegNext(flitTrigger(6)) & flitTrigger(6) ){
    flitCnt(7) := flitCnt(7) + 1.U
  }

  flitTrigger(8) := flitCnt(8) === 1.U
  when( ~RegNext(flitTrigger(7)) & flitTrigger(7) ){
    flitCnt(8) := flitCnt(8) + 1.U
  }

  for( j <- 0 until gp ) {

    val digitalFilter = downReg(0+j)
    val digitalIn = Wire( Vec(8, Bool()) )

    when(true.B){ upReg( 2+j ) := Cat( digitalIn.reverse  ) }

    for( i <- 0 until 8 ) {

      val flitter = RegInit(VecInit( Seq.fill(25){false.B}))
      val flitHi  = RegInit(0.U(5.W))

      digitalIn(i) := upReg( 2+j )(i)

      ( 0 until 9 ).map{ k => 
        when( digitalFilter === k.U ){
          when( flitTrigger(k) ){
            flitter(0) := in(i+8*j)
            (1 until 25).map{ k =>
              flitter(k) := flitter(k-1)
            }

            when( (~flitter(24) & ~in(i+8*j)) | (flitter(24) & in(i+8*j)) ){
              flitHi := flitHi
            } .elsewhen( ~flitter(24) & in(i+8*j) ){
              flitHi := flitHi + 1.U
            } .elsewhen( flitter(24) & ~in(i+8*j) ){
              flitHi := flitHi - 1.U
            }

            when( flitHi >= 20.U ){
              digitalIn(i) := true.B
            } .elsewhen( flitHi <= 5.U ){
              digitalIn(i) := false.B
            }      

            assert( flitHi <= 25.U )
            assert( flitter.count( (k:Bool) => k === true.B ) === flitHi )

          }
        }
      }
    }
  }

}




class DIn16 extends BackBoardSlvLocal
with BackBoardSlvStatusLed
with BackBoardSlvIn{
  def gp = 2
}







class BackBoardSlvOut16 extends BackBoardSlvLocal{
  val in  = IO(Input(UInt(32.W)))
  val out = IO(Output(UInt(32.W)))
  val oe  = IO(Output(UInt(32.W)))



  out := Cat( (0 until 4).map{i => downReg(i)}.reverse )
  oe  := Cat( (4 until 8).map{i => downReg(i)}.reverse )

  for( i <- 0 until 4 ) {
    upReg(i) := in( i*8+7,8*i )
  }
}


// trait LocalRegisters { this: BackBoardSlvBase =>
//   val led = IO(Output(UInt(3.W)))
//   val sw  = IO( Input(UInt(1.W)))



//   val digitalDir = RegInit(0.U(32.W))
//   val digitalOut = RegInit(0.U(32.W))
//   val digitalIn  = RegInit(VecInit(Seq.fill(32){false.B}))
//   val digitalFilter = RegInit(0.U(2.W))


//   val clk100usCnt = RegInit(0.U(13.W))

//   when( clk100usCnt < 5000.U ){
//     clk100usCnt := clk100usCnt + 1.U
//   } .otherwise{
//     clk100usCnt := 0.U
//   }

//   for( i <- 0 until 32 ) {
//     val hiCnt = RegInit( 0.U( 7.W ) )
//     val loCnt = RegInit( 0.U( 7.W ) )
//     val toCnt = RegInit( 0.U( 7.W ) )

//     when( digitalFilter === "b00".U ){
//       digitalIn(i) := sw
//     } .elsewhen( digitalFilter === "b01".U ){
//       when( clk100usCnt === 5000.U ){
//         when( toCnt === 10.U ){
//           hiCnt := 0.U
//           loCnt := 0.U
//           toCnt := 0.U
//           when( hiCnt >= 8.U & digitalIn(i) === false.B){ digitalIn(i) := true.B }
//           when( loCnt >= 8.U & digitalIn(i) === true.B) { digitalIn(i) := false.B }
//         } .elsewhen( toCnt > 10.U ){
//           hiCnt := 0.U
//           loCnt := 0.U
//           toCnt := 0.U
//         } .otherwise{
//           when(sw === true.B)  { hiCnt := hiCnt + 1.U }
//           when(sw === false.B) { loCnt := loCnt + 1.U }
//           toCnt := toCnt + 1.U
//         }
//       }
//     } .elsewhen( digitalFilter === "b10".U ){
//       when( clk100usCnt === 5000.U ){
//         when( toCnt === 40.U ){
//           hiCnt := 0.U
//           loCnt := 0.U
//           toCnt := 0.U
//           when( hiCnt >= 32.U & digitalIn(i) === false.B){ digitalIn(i) := true.B }
//           when( loCnt >= 32.U & digitalIn(i) === true.B) { digitalIn(i) := false.B }
//         } .elsewhen( toCnt > 40.U ){
//           hiCnt := 0.U
//           loCnt := 0.U
//           toCnt := 0.U
//         } .otherwise{
//           when(sw === true.B)  { hiCnt := hiCnt + 1.U }
//           when(sw === false.B) { loCnt := loCnt + 1.U }
//           toCnt := toCnt + 1.U
//         }
//       }
//     } .elsewhen( digitalFilter === "b11".U ){
//       when( clk100usCnt === 5000.U ){
//         when( toCnt === 80.U ){
//           hiCnt := 0.U
//           loCnt := 0.U
//           toCnt := 0.U
//           when( hiCnt >= 64.U & digitalIn(i) === false.B){ digitalIn(i) := true.B }
//           when( loCnt >= 64.U & digitalIn(i) === true.B) { digitalIn(i) := false.B }
//         } .elsewhen( toCnt > 80.U ){
//           hiCnt := 0.U
//           loCnt := 0.U
//           toCnt := 0.U
//         } .otherwise{
//           when(sw === true.B)  { hiCnt := hiCnt + 1.U }
//           when(sw === false.B) { loCnt := loCnt + 1.U }
//           toCnt := toCnt + 1.U
//         }
//       }
//     }
//   }




  
//   val pluseCnt = RegInit(0.U(32.W))

//   val pluseShift = ShiftRegisters( sw, 3, false.B, true.B )
//   when( ~pluseShift(2).asBool & pluseShift(1).asBool ){
//     pluseCnt := pluseCnt + 1.U
//   }

//   val pluseAutoCnt = RegInit(0.U(32.W))
//   val pluseAutoFre = RegInit(0.U(32.W))
//   when( clk100usCnt === 5000.U ){
//     pluseAutoCnt := 0.U
//     pluseAutoFre := pluseAutoCnt
//   } .elsewhen( ~pluseShift(2).asBool & pluseShift(1).asBool ){
//     pluseAutoCnt := pluseAutoCnt + 1.U
//   }

//   val qeiA = IO(Input(Bool()))
//   val qeiB = IO(Input(Bool()))

//   val qeiAShift = ShiftRegisters( qeiA, 2, false.B, true.B )
//   val qeiBShift = ShiftRegisters( qeiB, 3, false.B, true.B )

//   val qeiCnt = RegInit(0.U(32.W))
//   val qeiAutoCnt = RegInit(0.U(32.W))
//   val qeiAutoFre = RegInit(0.U(32.W))

//   when( ~qeiBShift(2) & qeiBShift(1) ){
//     qeiCnt := Mux( qeiAShift(1), qeiCnt + 1.U, qeiCnt - 1.U )
//     qeiAutoCnt := Mux( qeiAShift(1), qeiCnt + 1.U, qeiCnt - 1.U )
//   }


//   when( clk100usCnt === 5000.U ){
//     qeiAutoCnt := 0.U
//     qeiAutoFre := qeiAutoCnt
//   } .elsewhen( ~qeiBShift(2) & qeiBShift(1) ){
//     qeiAutoCnt := Mux( qeiAShift(1), qeiAutoCnt + 1.U, qeiAutoCnt - 1.U )
//   }
  
  
//   registersRD := Mux1H(Seq(
//     (upStreamReq.io.latDat.bits.register === 0.U) -> digitalDir,
//     (upStreamReq.io.latDat.bits.register === 1.U) -> digitalIn.asUInt,
//     (upStreamReq.io.latDat.bits.register === 2.U) -> digitalFilter,
//     (upStreamReq.io.latDat.bits.register === 3.U) -> pluseCnt,
//     (upStreamReq.io.latDat.bits.register === 4.U) -> pluseAutoFre,
//     (upStreamReq.io.latDat.bits.register === 5.U) -> qeiCnt,
//     (upStreamReq.io.latDat.bits.register === 6.U) -> qeiAutoFre,
//   ))

//   when( upStreamReq.io.latDat.fire & upStreamReq.io.latDat.bits.address(5,1) === io.localHost & upStreamReq.io.latDat.bits.address.extract(0) === 1.U ){
//     when(upStreamReq.io.latDat.bits.register === 0.U){
//       digitalDir := upStreamReq.io.latDat.bits.data
//     }
//     when(upStreamReq.io.latDat.bits.register === 1.U){
//       digitalOut := upStreamReq.io.latDat.bits.data
//     }
//     when(upStreamReq.io.latDat.bits.register === 2.U){
//       digitalFilter := upStreamReq.io.latDat.bits.data
//     }
//     when(upStreamReq.io.latDat.bits.register === 3.U){
//       pluseCnt := upStreamReq.io.latDat.bits.data
//     }
//     when(upStreamReq.io.latDat.bits.register === 4.U){
//       ;
//     }
//     when(upStreamReq.io.latDat.bits.register === 5.U){
//       qeiCnt := upStreamReq.io.latDat.bits.data
//     }
//     when(upStreamReq.io.latDat.bits.register === 6.U){
//       ;
//     }
//   }




//   led := digitalOut(2,0)
//   // digitalIn := sw
// }