eb001/src/main/scala/backBoard/shin/SlaveParser.scala

package BACK

import chisel3._
import chisel3.util._


class FrameHeader extends Bundle{
  val frameLenAim  = UInt(12.W) //帧长度目标
  val frameStyle   = UInt(2.W)  //包类型
  val frameInfo    = UInt(16.W) //其它信息，如probe
}

class SubMsgHeader extends Bundle{
  val devIndex = UInt(14.W) // 子报文中设备索引
  val style    = UInt(2.W)  // 子报文类型
  val address  = UInt(16.W) //子报文地址
  val operator = UInt(4.W)  //子报文命令类型
  val length   = UInt(12.W) //子报文负载长度
  val workCnt  = UInt(16.W) //子报文工作计数

  def isSeqIndex = style === 0.U
  def isLgcIndex = style === 2.U
}



// class ShareSRAMIO extends Bundle{
//   val addr  = Input(UInt(15.W))
//   val dataw  = Input( UInt(8.W) )
//   val datar  = Output( UInt(8.W) )
//   val enw    = Input(Bool())
//   val enr    = Input(Bool())
// }



class SlaveParserIO extends Bundle{
  val downIn  = Flipped( Decoupled(new AXIS_Bundle(8)) )
  val downOut = Decoupled(new AXIS_Bundle(8))

  val upIn  = Flipped( Decoupled(new AXIS_Bundle(8)) )
  val upOut = Decoupled(new AXIS_Bundle(8))

  val sram_w = Vec( 4, Flipped(new SRAM2kWRIO))
  val sram_r = Vec( 4, Flipped(new SRAM2kRDIO))

  val dSMenq = Output( Vec(4, Bool()) )
  val uSMdeq = Output( Vec(4, Bool()) )




  val localDevIndex = Output(UInt(16.W))

  //开放链路寄存器组给interface
  // val isDevOnLeft        = Output(UInt(2.W))
  // val isDevOnLeftModify  = Output(Bool())
  // val indexOfLeftDev     = Output(UInt(14.W))
  val isDevOnRight       = Output(UInt(2.W))
  val isDevOnRightModify = Output(Bool())
  val indexOfRightDev    = Output(UInt(14.W))


  val mstDeltaTimeStamp = Output(UInt(32.W))
  val slvDeltaTime = Output(UInt(32.W))
  val deltaFinal        = Output(UInt(32.W))

  val isLoop = Output(Bool())

  val cReg = Input(new CommonRegisterBundle)
  val sReg = Input(new SlaveRegisterBundle)

  val lvds  = new RegAccessInterfaceIO

  val intHWTrig   = Output(Vec(2, Bool()))
  val intHWClr    = Input (Vec(2, Bool()))
}

abstract class SlaveParserBase extends Module{
  val io: SlaveParserIO = IO(new SlaveParserIO)

  val sReg = io.sReg



  val FRAME_STYLE_COMMON = 0.U
  val FRAME_STYLE_PROBE  = 1.U

  val SUBMSG_OPERATOR_UNIREAD    = 0.U
  val SUBMSG_OPERATOR_UNIWRITE   = 1.U
  val SUBMSG_OPERATOR_UNIRDWR    = 2.U
  val SUBMSG_OPERATOR_INDEX      = "hb".U
  val SUBMSG_OPERATOR_SYNC       = "hc".U
  val SUBMSG_OPERATOR_BOARDREAD  = "hd".U
  val SUBMSG_OPERATOR_BOARDWRITE = "he".U
  val SUBMSG_OPERATOR_BOARDRDWR  = "hf".U


  val STATE_IDLE                = 0.U //空闲
  val STATE_HEADER              = 1.U //长度/ /保留2bits //包类型
  val STATE_SUBMSG_HEADER       = 2.U //子报文头
  val STATE_PAYLOAD_DATA        = 3.U //子报文数据
  val STATE_CRC                 = 4.U //CRC校验
  val STATE_ERROR               = 5.U //
  val STATE_WAIT                = 6.U



  val downRecParser = Module(new SlaveRecParser)
  val upRecParser   = Module(new SlaveRecParser)
  val downSendGen = Module(new SlaveSendGen)
  val upSendGen   = Module(new SlaveSendGen)

  val isReadyToProbe  = RegInit(false.B)
  val isAckProbe = RegInit(false.B)
  val isLastDevice: Bool = RegInit(true.B)

  // val isDevOnLeft        = RegInit(0.U(2.W));  io.isDevOnLeft        := isDevOnLeft
  // val isDevOnLeftModify  = RegInit(false.B);   io.isDevOnLeftModify  := isDevOnLeftModify
  // val indexOfLeftDev     = RegInit(0.U(14.W)); io.indexOfLeftDev     := indexOfLeftDev
  io.isDevOnRight       := Mux( isLastDevice, "b00".U, "b01".U )
  val isDevOnRightModify = RegInit(false.B);   io.isDevOnRightModify := isDevOnRightModify
  val indexOfRightDev    = RegInit(0.U(14.W)); io.indexOfRightDev    := indexOfRightDev

  val localDevIndex = RegInit(0.U(14.W)); io.localDevIndex := localDevIndex //当前设备索引








  //处理主报文


  downSendGen.io.frameReq.valid := downRecParser.io.frameReq.fire
  assert( ~(downSendGen.io.frameReq.valid & ~downSendGen.io.frameReq.ready) )

  {
    downSendGen.io.frameReq.bits  := downRecParser.io.frameReq.bits
    //voerride
    downSendGen.io.frameReq.bits.frameInfo := localDevIndex
  }
  

  val upFrameProbeInfo: FrameHeader = Wire(new FrameHeader)
  upFrameProbeInfo.frameLenAim := 0.U                //帧长度目标
  upFrameProbeInfo.frameStyle  := FRAME_STYLE_PROBE  //包类型
  upFrameProbeInfo.frameInfo   := localDevIndex      //其它信息，如probe

  upSendGen.io.frameReq.valid :=
  (upRecParser.io.frameReq.fire & upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_COMMON) |
  isAckProbe

  assert( ~(upSendGen.io.frameReq.valid & ~upSendGen.io.frameReq.ready) )


  assert( ~(upRecParser.io.frameReq.fire & isAckProbe), "Assert Failed, Check Softwave, Probe is Sent while transfering!\n" )

  upSendGen.io.frameReq.bits := Mux1H(Seq(
    upRecParser.io.frameReq.fire -> upRecParser.io.frameReq.bits,      //上行转发
    isAckProbe                   -> upFrameProbeInfo, //上行探针
  ))







////////////////////////////////////////

  //子报文
  val isDownSubMsgValid = for( _ <- 0 until 2 ) yield { RegInit(false.B) }
  val isUpSubMsgValid   = for( _ <- 0 until 2 ) yield { RegInit(false.B) }





  //接收子报文

  val downSubMsgInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTxInfo) } //子报文头
  val upSubMsgInfo   = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTxInfo) }



  val downRecFifo = for( _ <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 20)) } //子报文负载
  val upRecFifo   = for( _ <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 20)) }

  val isDownRecPing = RegInit(false.B)
  val isUpRecPing   = RegInit(false.B)



  //下行接收
  when( downRecParser.io.subMsgReq.fire ){
    when( isDownRecPing ){
      downSubMsgInfo(0).devIndex := downRecParser.io.subMsgReq.bits.devIndex
      downSubMsgInfo(0).style    := downRecParser.io.subMsgReq.bits.style
      downSubMsgInfo(0).address  := downRecParser.io.subMsgReq.bits.address
      downSubMsgInfo(0).operator := downRecParser.io.subMsgReq.bits.operator
      downSubMsgInfo(0).length   := downRecParser.io.subMsgReq.bits.length
      downSubMsgInfo(0).workCnt  := downRecParser.io.subMsgReq.bits.workCnt
      downSubMsgInfo(0).source := 0.U
    } .otherwise{ //pong
      downSubMsgInfo(1).devIndex := downRecParser.io.subMsgReq.bits.devIndex
      downSubMsgInfo(1).style    := downRecParser.io.subMsgReq.bits.style
      downSubMsgInfo(1).address  := downRecParser.io.subMsgReq.bits.address
      downSubMsgInfo(1).operator := downRecParser.io.subMsgReq.bits.operator
      downSubMsgInfo(1).length   := downRecParser.io.subMsgReq.bits.length
      downSubMsgInfo(1).workCnt  := downRecParser.io.subMsgReq.bits.workCnt
      downSubMsgInfo(1).source   := 1.U
    }
  }




  when( ~isDownRecPing ){ //req fire 后 已经反相
    downRecFifo(0).io.enq.valid := downRecParser.io.data.valid
    downRecFifo(0).io.enq.bits  := downRecParser.io.data.bits
    downRecParser.io.data.ready := downRecFifo(0).io.enq.ready

    downRecFifo(1).io.enq.valid := false.B
    downRecFifo(1).io.enq.bits  := 0.U

  } .otherwise{
    downRecFifo(0).io.enq.valid := false.B
    downRecFifo(0).io.enq.bits  := 0.U

    downRecFifo(1).io.enq.valid := downRecParser.io.data.valid
    downRecFifo(1).io.enq.bits  := downRecParser.io.data.bits
    downRecParser.io.data.ready := downRecFifo(1).io.enq.ready
  }





  //上行接收
  when( upRecParser.io.subMsgReq.fire ){
    when( isUpRecPing ){
      upSubMsgInfo(0).devIndex := upRecParser.io.subMsgReq.bits.devIndex
      upSubMsgInfo(0).style    := upRecParser.io.subMsgReq.bits.style
      upSubMsgInfo(0).address  := upRecParser.io.subMsgReq.bits.address
      upSubMsgInfo(0).operator := upRecParser.io.subMsgReq.bits.operator
      upSubMsgInfo(0).length   := upRecParser.io.subMsgReq.bits.length
      upSubMsgInfo(0).workCnt  := upRecParser.io.subMsgReq.bits.workCnt
      upSubMsgInfo(0).source := 0.U
    } .otherwise{
      upSubMsgInfo(1).devIndex := upRecParser.io.subMsgReq.bits.devIndex
      upSubMsgInfo(1).style    := upRecParser.io.subMsgReq.bits.style
      upSubMsgInfo(1).address  := upRecParser.io.subMsgReq.bits.address
      upSubMsgInfo(1).operator := upRecParser.io.subMsgReq.bits.operator
      upSubMsgInfo(1).length   := upRecParser.io.subMsgReq.bits.length
      upSubMsgInfo(1).workCnt  := upRecParser.io.subMsgReq.bits.workCnt
      upSubMsgInfo(1).source := 1.U
    }
  }








  //子报文下行发送

  val isDownSendPing = RegInit(false.B)
  val isUpSendPing   = RegInit(false.B)



  downSendGen.io.subMsgReq.valid := 
    ( isDownSendPing & isDownSubMsgValid(0) ) | (~isDownSendPing & isDownSubMsgValid(1))

  downSendGen.io.subMsgReq.bits := Mux( isDownSendPing, downSubMsgInfo(0), downSubMsgInfo(1) )

  when( downSendGen.io.subMsgReq.fire ){ //ready
    isDownSendPing := ~isDownSendPing
    when( isDownSendPing ){
      assert( isDownSubMsgValid(0) )
      isDownSubMsgValid(0) := false.B
    } .otherwise{
      assert( isDownSubMsgValid(1) )
      isDownSubMsgValid(1) := false.B
    }
  } .elsewhen( downRecParser.io.subMsgReq.fire ){
    isDownRecPing := ~isDownRecPing
    when( isDownRecPing ){
      assert( ~isDownSubMsgValid(0) )
      isDownSubMsgValid(0) := true.B
    } .otherwise{
      assert( ~isDownSubMsgValid(1) )
      isDownSubMsgValid(1) := true.B
    }
  }


  downRecFifo(0).io.deq <> downSendGen.io.data(0)
  downRecFifo(1).io.deq <> downSendGen.io.data(1)

  downRecParser.io.resp := ( downRecParser.io.stateCurr === STATE_WAIT ) & (~isDownSubMsgValid(0) & ~isDownSubMsgValid(1))


  //子报文上行发送


  upSendGen.io.subMsgReq.valid := 
    (  isUpSendPing & isUpSubMsgValid(0) ) |
    ( ~isUpSendPing & isUpSubMsgValid(1) )

  upSendGen.io.subMsgReq.bits := Mux( isUpSendPing, upSubMsgInfo(0), upSubMsgInfo(1) )
  
  when( upSendGen.io.subMsgReq.fire ){ //ready
    isUpSendPing := ~isUpSendPing
    when( isUpSendPing ){
      assert( isUpSubMsgValid(0) )
      isUpSubMsgValid(0) := false.B
    } .otherwise{
      assert( isUpSubMsgValid(1) )
      isUpSubMsgValid(1) := false.B
    }
  }.elsewhen( upRecParser.io.subMsgReq.fire ){
    isUpRecPing := ~isUpRecPing
    when( isUpRecPing ){
      assert( ~isUpSubMsgValid(0) )
      isUpSubMsgValid(0) := true.B
    } .otherwise{
      assert( ~isUpSubMsgValid(1) )
      isUpSubMsgValid(1) := true.B
    }
  }

  upRecFifo(0).io.deq <> upSendGen.io.data(0)
  upRecFifo(1).io.deq <> upSendGen.io.data(1)

  upRecParser.io.resp := ( upRecParser.io.stateCurr === STATE_WAIT ) & (~isUpSubMsgValid(0) & ~isUpSubMsgValid(1))

}















trait SlaveParserIndex{ this: SlaveParserBase =>
 //下行接收
  when( downRecParser.io.subMsgReq.fire &
        downRecParser.io.subMsgReq.bits.devIndex === 0.U &
        downRecParser.io.subMsgReq.bits.style === 0.U &
        downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_INDEX ){ //设置顺序地址
    localDevIndex := downRecParser.io.subMsgReq.bits.workCnt + 1.U
    indexOfRightDev    := Mux(isLastDevice, 0.U, downRecParser.io.subMsgReq.bits.workCnt + 2.U)
    when( isDownRecPing ){
      downSubMsgInfo(0).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U
    } .otherwise{ //pong
      downSubMsgInfo(1).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U
    }
  }


  //上行接收 获取右侧索引号

}





trait SlaveParserRW{ this: SlaveParserBase =>

  // val isSeqIndexMatch = 
  //   (downRecParser.io.subMsgReq.bits.isSeqIndex & downRecParser.io.subMsgReq.bits.devIndex === localDevIndex)

  // val downLgcAddress  = Cat( downRecParser.io.subMsgReq.bits.devIndex, downRecParser.io.subMsgReq.bits.address )
  // val isLgcIndexMatch = 
  //   (downRecParser.io.subMsgReq.bits.isLgcIndex &




  //下行接收
  when( downRecParser.io.subMsgReq.fire ){
    when( isDownRecPing ){
      //override
      when(
        ( ( (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE)   | (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR)   ) & downRecParser.io.subMsgReq.bits.devIndex === localDevIndex ) |
        ( ( (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDWRITE) | (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR) ) )
      ) { //自身包//写操作或读写操作)
        downSubMsgInfo(0).workCnt  := downRecParser.io.subMsgReq.bits.workCnt + 1.U
      }

    } .otherwise{ //pong
      //override
      when(
        ( ( (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE  ) | (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR  ) ) & downRecParser.io.subMsgReq.bits.devIndex === localDevIndex ) |
        ( ( (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDWRITE) | (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR) ) )
      ) { //自身包//写操作或读写操作 )
        downSubMsgInfo(1).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U
      }
    }
  }



  //写入 SM或寄存器空间

  val addrw = Reg(UInt(15.W))
  val logicAddrwNext = Wire( UInt(30.W) )
  val logicAddrw = RegNext(logicAddrwNext)

  val isWRReg = (addrw(14,11) === "b0000".U)
  val isWRSM0 = (addrw(14,11) === "b0001".U)
  val isWRSM2 = (addrw(14,11) === "b0011".U)
  val isWRSM4 = (addrw(14,11) === "b0101".U)
  val isWRSM6 = (addrw(14,11) === "b0111".U)

  val downTransLenCnt = RegInit(0.U)

  val isWrite = (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相
    ( ~isDownRecPing & ( (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE)   | (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR  ) ) & ( (downSubMsgInfo(0).isSeqIndex & downSubMsgInfo(0).devIndex === localDevIndex) || ( downSubMsgInfo(0).isLgcIndex & downTransLenCnt =/= 0.U) ) ) |
    (  isDownRecPing & ( (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE)   | (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR  ) ) & ( (downSubMsgInfo(1).isSeqIndex & downSubMsgInfo(1).devIndex === localDevIndex) || ( downSubMsgInfo(1).isLgcIndex & downTransLenCnt =/= 0.U) ) ) |
    ( ~isDownRecPing & ( (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR) )                                                 ) |
    (  isDownRecPing & ( (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR) )                                                 )
  )


  val isDownLgcAddrwAcquireTrans = //是否触发地址转换
    (downTransLenCnt === 0.U) & ( (0 until 8).map{ i =>
      sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_WR || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrwNext === sReg.ebmmu(i).lAddr)
    }.reduce(_|_))

  val acquireDownPhyAddrw = Mux1H( //选择一个ebmmu
    (0 until 8).map{ i =>
      (sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_WR || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrwNext === sReg.ebmmu(i).lAddr)) ->
      sReg.ebmmu(i).pAddr
    }
  )

  val acquireDownTransLen = Mux1H( //选择一个ebmmu
    (0 until 8).map{ i =>
      (sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_WR || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrwNext === sReg.ebmmu(i).lAddr)) ->
      sReg.ebmmu(i).length
    }
  )

  when( isDownLgcAddrwAcquireTrans ){ //装填计数器
    downTransLenCnt := acquireDownTransLen
  } .elsewhen( downRecParser.io.data.fire & downTransLenCnt =/= 0.U){
    downTransLenCnt := downTransLenCnt - 1.U
  }

  //组合逻辑
  when( downRecParser.io.subMsgReq.fire & (
    (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgReq.bits.isLgcIndex 
  )){//组合逻辑
    logicAddrwNext := Cat( downRecParser.io.subMsgReq.bits.devIndex, downRecParser.io.subMsgReq.bits.address )
  } .elsewhen( downRecParser.io.data.fire & (
    ( ~isDownRecPing & ( (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downSubMsgInfo(0).isLgcIndex ) |
    (  isDownRecPing & ( (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downSubMsgInfo(1).isLgcIndex )
  )){//组合逻辑
    logicAddrwNext := logicAddrw + 1.U
  } .otherwise{//组合逻辑
    logicAddrwNext := logicAddrw
  }


  when( downRecParser.io.subMsgReq.fire ){ //子包头装填
    when(
      ( (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE   | downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgReq.bits.isSeqIndex & downRecParser.io.subMsgReq.bits.devIndex === localDevIndex ) |
      (  downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDWRITE | downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR )
    ){ //常规寻址
      addrw := downRecParser.io.subMsgReq.bits.address
    } .elsewhen( (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgReq.bits.isLgcIndex ){ //逻辑寻址
      addrw := acquireDownPhyAddrw
    }
  } .elsewhen( isWrite & downRecParser.io.data.fire ){
    when(
      ( (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE   | downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgReq.bits.isSeqIndex & downRecParser.io.subMsgReq.bits.devIndex === localDevIndex ) |
      (  downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDWRITE | downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR )
    ){
      addrw := addrw + 1.U
    } .elsewhen( (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgReq.bits.isLgcIndex ){
      addrw := Mux( downTransLenCnt === 0.U, Mux(isDownLgcAddrwAcquireTrans, acquireDownPhyAddrw, 0.U), addrw + 1.U )
    }
  }




  io.lvds.isEnW   := isWrite & isWRReg & downRecParser.io.data.fire
  io.lvds.dataw   := downRecParser.io.data.bits

  io.sram_w(0).enw   := isWrite & isWRSM0 & downRecParser.io.data.fire
  io.sram_w(0).addrw := addrw(10,0)
  io.sram_w(0).dataw := downRecParser.io.data.bits

  io.sram_w(1).enw   := isWrite & isWRSM2 & downRecParser.io.data.fire
  io.sram_w(1).addrw := addrw(10,0)
  io.sram_w(1).dataw := downRecParser.io.data.bits

  io.sram_w(2).enw   := isWrite & isWRSM4 & downRecParser.io.data.fire
  io.sram_w(2).addrw := addrw(10,0)
  io.sram_w(2).dataw := downRecParser.io.data.bits

  io.sram_w(3).enw   := isWrite & isWRSM6 & downRecParser.io.data.fire
  io.sram_w(3).addrw := addrw(10,0)
  io.sram_w(3).dataw := downRecParser.io.data.bits


  



  //上行接收
  when( upRecParser.io.subMsgReq.fire ){
    when( isUpRecPing ){
      //override
      when( 
        ( ( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD  ) | (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR  ) ) & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex ) |
        ( ( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD) | (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR) ) )
      ){ //自身包//读或读写
        upSubMsgInfo(0).workCnt  := upRecParser.io.subMsgReq.bits.workCnt + 1.U
      }
    } .otherwise{
      //override
      when(
        ( ( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD  ) | (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR  ) ) & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex ) |
        ( ( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD) | (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR) ) )
      ){ //自身包//读或读写 )
        upSubMsgInfo(1).workCnt  := upRecParser.io.subMsgReq.bits.workCnt + 1.U
      }
    }
  }





  val upTransLenCnt = RegInit(0.U)


  val addrr = Reg(UInt(15.W))  
  val logicAddrrNext = Wire( UInt(30.W) )
  val logicAddrr = RegNext(logicAddrrNext)


  val isUpLgcAddrrAcquireTrans = //是否触发地址转换
    (upTransLenCnt === 0.U) & ( (0 until 8).map{ i =>
      sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_RD || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrrNext === sReg.ebmmu(i).lAddr)
    }.reduce(_|_))

  val acquireUpPhyAddrr = Mux1H( //选择一个ebmmu
    (0 until 8).map{ i =>
      (sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_RD || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrrNext === sReg.ebmmu(i).lAddr)) ->
      sReg.ebmmu(i).pAddr
    }
  )

  val acquireUpTransLen = Mux1H( //选择一个ebmmu
    (0 until 8).map{ i =>
      (sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_RD || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrrNext === sReg.ebmmu(i).lAddr)) ->
      sReg.ebmmu(i).length
    }
  )

  when( isUpLgcAddrrAcquireTrans ){ //装填计数器
    upTransLenCnt := acquireUpTransLen
  } .elsewhen( upRecParser.io.data.fire & upTransLenCnt =/= 0.U){
    upTransLenCnt := upTransLenCnt - 1.U
  }

  //组合逻辑
  when( upRecParser.io.subMsgReq.fire & (
    (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex 
  )){//组合逻辑
    logicAddrrNext := Cat( upRecParser.io.subMsgReq.bits.devIndex, upRecParser.io.subMsgReq.bits.address )
  } .elsewhen( upRecParser.io.data.fire & (
    (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgInfo(0).isLgcIndex ) |
    ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgInfo(1).isLgcIndex )
  ) ){//组合逻辑
    logicAddrrNext := logicAddrr + 1.U
  } .otherwise{//组合逻辑
    logicAddrrNext := logicAddrr
  }


  val isRDReg = addrr(14,11) === "b0000".U
  val isRDSM1 = addrr(14,11) === "b0010".U
  val isRDSM3 = addrr(14,11) === "b0100".U
  val isRDSM5 = addrr(14,11) === "b0110".U
  val isRDSM7 = addrr(14,11) === "b1000".U


  val isSeqRead = 
    ((upRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & (
      (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD   | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR   ) & ((upSubMsgInfo(0).isSeqIndex & upSubMsgInfo(0).devIndex === localDevIndex) )) |
      ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD   | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR   ) & ((upSubMsgInfo(1).isSeqIndex & upSubMsgInfo(1).devIndex === localDevIndex) )) |
      (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR )                                             ) |
      ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR )                                             )
    )
  ) & ( (RegNext(upRecParser.io.stateCurr) =/= STATE_PAYLOAD_DATA) | upRecParser.io.data.fire )

  val isLgcRead = 
    ((upRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & (
      (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( (upSubMsgInfo(0).isLgcIndex & upTransLenCnt =/= 0.U ) )) |
      ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( (upSubMsgInfo(1).isLgcIndex & upTransLenCnt =/= 0.U ) ))
    )
  ) & ( RegNext(isUpLgcAddrrAcquireTrans) | upRecParser.io.data.fire )

  val isLvdsEnR = isSeqRead | isLgcRead 

  when( upRecParser.io.subMsgReq.fire){
    when(
      ((upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD   | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR  ) & (upRecParser.io.subMsgReq.bits.isSeqIndex & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex)) |
      ( upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR)
    ){
      addrr := upRecParser.io.subMsgReq.bits.address
    } .elsewhen( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex ){
      addrr := acquireUpPhyAddrr
    }
  } .elsewhen( isUpLgcAddrrAcquireTrans ){
    when( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex ){
      addrr := acquireUpPhyAddrr
    }
  }
  .elsewhen( isLvdsEnR ){
    assert(~isUpLgcAddrrAcquireTrans)
    when( 
      ((upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD   | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR  ) & (upRecParser.io.subMsgReq.bits.isSeqIndex & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex)) |
      ( upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR)
    ){
      addrr := addrr + 1.U
    } .elsewhen( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex ){
      addrr := Mux( upTransLenCnt === 0.U, 0.U, addrr + 1.U )
    }
  }

  val upStreamData = Mux1H(Seq(
    isRDReg      -> io.lvds.datar,
    isRDSM1      -> io.sram_r(0).datar,
    isRDSM3      -> io.sram_r(1).datar,
    isRDSM5      -> io.sram_r(2).datar,
    isRDSM7      -> io.sram_r(3).datar,
  ))


  when( ~isUpRecPing ){ //req fire 后 已经反相
    upRecFifo(0).io.enq.valid := upRecParser.io.data.valid
    upRecFifo(0).io.enq.bits  := 
      Mux( 
           ( upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD   | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR   ) & ((upSubMsgInfo(0).isSeqIndex & upSubMsgInfo(0).devIndex === localDevIndex) | (upSubMsgInfo(0).isLgcIndex & upTransLenCnt =/= 0.U)), upStreamData,
        Mux( upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR, upStreamData | upRecParser.io.data.bits,
          upRecParser.io.data.bits )
      )
      upRecParser.io.data.ready := upRecFifo(0).io.enq.ready

    upRecFifo(1).io.enq.valid := false.B
    upRecFifo(1).io.enq.bits  := 0.U
  } .otherwise{
    upRecFifo(0).io.enq.valid := false.B
    upRecFifo(0).io.enq.bits  := 0.U

    upRecFifo(1).io.enq.valid := upRecParser.io.data.valid
    upRecFifo(1).io.enq.bits  :=
      Mux( 
           ( upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD   | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR   ) & ((upSubMsgInfo(1).isSeqIndex & upSubMsgInfo(1).devIndex === localDevIndex) | (upSubMsgInfo(1).isLgcIndex & upTransLenCnt =/= 0.U)), upStreamData,
        Mux( upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR, upStreamData | upRecParser.io.data.bits,
          upRecParser.io.data.bits
        )
      )
      upRecParser.io.data.ready := upRecFifo(1).io.enq.ready

  }




    
  

  io.lvds.addrr := addrr(10,0)
  io.lvds.addrw := addrw(10,0)


  // assert( ~(isRead & isWrite) )
  


  io.lvds.isEnR    := isRDReg & isLvdsEnR
  io.sram_r(0).enr := isRDSM1 & isLvdsEnR
  io.sram_r(1).enr := isRDSM3 & isLvdsEnR
  io.sram_r(2).enr := isRDSM5 & isLvdsEnR
  io.sram_r(3).enr := isRDSM7 & isLvdsEnR

  io.sram_r(0).addrr := addrr(10,0)
  io.sram_r(1).addrr := addrr(10,0)
  io.sram_r(2).addrr := addrr(10,0)
  io.sram_r(3).addrr := addrr(10,0)


  io.dSMenq(0) := io.sram_w(0).enw & isWRSM0 & (io.cReg.smTrigLen(0) - 1.U) === addrw(10,0)
  io.uSMdeq(0) := isLvdsEnR  & isRDSM1 & (io.cReg.smTrigLen(1) - 1.U + 1.U) === addrr(10,0)
  io.dSMenq(1) := io.sram_w(1).enw & isWRSM2 & (io.cReg.smTrigLen(2) - 1.U) === addrw(10,0)
  io.uSMdeq(1) := isLvdsEnR  & isRDSM3 & (io.cReg.smTrigLen(3) - 1.U + 1.U) === addrr(10,0)
  io.dSMenq(2) := io.sram_w(2).enw & isWRSM4 & (io.cReg.smTrigLen(4) - 1.U) === addrw(10,0)
  io.uSMdeq(2) := isLvdsEnR  & isRDSM5 & (io.cReg.smTrigLen(5) - 1.U + 1.U) === addrr(10,0)
  io.dSMenq(3) := io.sram_w(3).enw & isWRSM6 & (io.cReg.smTrigLen(6) - 1.U) === addrw(10,0)
  io.uSMdeq(3) := isLvdsEnR  & isRDSM7 & (io.cReg.smTrigLen(7) - 1.U + 1.U) === addrr(10,0)


}


trait SlaveParserSync{ this: SlaveParserBase =>
  //下行接收
  when( downRecParser.io.subMsgReq.fire ){
    when( isDownRecPing ){
      //override
      when( downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_SYNC ) { //同步包
        downSubMsgInfo(0).workCnt  := downRecParser.io.subMsgReq.bits.workCnt + 1.U
      }

    } .otherwise{ //pong
      //override
      when( downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_SYNC  ) { //同步包 )
        downSubMsgInfo(1).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U
      }
    }
  }



  val downTimeStamp = Reg(UInt(64.W)) //下行本地时间戳寄存器 
  val upTimeStamp   = Reg(UInt(64.W)) //上行本地时间戳寄存器
  val mstTimeStamp  = Reg(UInt(64.W)) //主站时间戳
  val mstDeltaTimeStamp = Reg(UInt(32.W)); io.mstDeltaTimeStamp := mstDeltaTimeStamp //主站时间戳差值
  val slvDeltaTimeStamp = Reg(UInt(32.W)); io.slvDeltaTime := slvDeltaTimeStamp //从站时间戳差值

  val mstSlvDeltaTimeStamp = Reg(UInt(32.W)) //主发从接时间差(中间变量)
  val deltaMstSlvDeltaTimeStamp = Reg(UInt(32.W)) //主差从差时间差(中间变量)
  val deltaFinal = Reg(UInt(32.W)); io.deltaFinal := deltaFinal //当前时间戳与主站时间差


  // val recoTimeStamp = Reg(UInt(64.W)) //时钟补偿寄存器

  // dontTouch(recoTimeStamp)

  // recoTimeStamp = io.timeStamp + deltaFinal
  // recoTimeStamp = io.timeStamp + mstSlvDeltaTimeStamp         + deltaMstSlvDeltaTimeStamp
  // recoTimeStamp = io.timeStamp + mstTimeStamp - downTimeStamp + (mstDeltaTimeStamp - slvDeltaTimeStamp            ) >> 1
  // recoTimeStamp = io.timeStamp + mstTimeStamp - downTimeStamp + (mstDeltaTimeStamp - (upTimeStamp - downTimeStamp)) >> 1


  //更新下行本地时间戳寄存器
  when( downRecParser.io.frameReq.fire & downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_COMMON ){
    downTimeStamp := io.cReg.timeStamp
  }

  //更新上行本地时间戳寄存器
  when( upRecParser.io.frameReq.fire & upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_COMMON ){
    upTimeStamp := io.cReg.timeStamp
    slvDeltaTimeStamp := io.cReg.timeStamp - downTimeStamp
  }

  //下行接收
  val isSync = (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相
    ( ~isDownRecPing & downSubMsgInfo(0).devIndex === 0.U & downSubMsgInfo(0).operator === SUBMSG_OPERATOR_SYNC ) |
    (  isDownRecPing & downSubMsgInfo(1).devIndex === 0.U & downSubMsgInfo(1).operator === SUBMSG_OPERATOR_SYNC )
  )

  val syncCnt = Reg(UInt(4.W))

  when( downRecParser.io.rec.fire ){
    when( isSync ){
      syncCnt := syncCnt + 1.U
    } .otherwise{
      syncCnt := 0.U
    }    
  }


  when( isSync & downRecParser.io.rec.fire ){
    when( syncCnt === 0.U ){
      mstTimeStamp := Cat( mstTimeStamp(63, 8), downRecParser.io.data.bits )
    } .elsewhen( syncCnt === 1.U ){
      mstTimeStamp := Cat( mstTimeStamp(63,16), downRecParser.io.data.bits, mstTimeStamp(7,0) )
    } .elsewhen( syncCnt === 2.U ){
      mstTimeStamp := Cat( mstTimeStamp(63,24), downRecParser.io.data.bits, mstTimeStamp(15,0) )
    } .elsewhen( syncCnt === 3.U ){
      mstTimeStamp := Cat( mstTimeStamp(63,32), downRecParser.io.data.bits, mstTimeStamp(23,0) )
    } .elsewhen( syncCnt === 4.U ){
      mstTimeStamp := Cat( mstTimeStamp(63,40), downRecParser.io.data.bits, mstTimeStamp(31,0) )
    } .elsewhen( syncCnt === 5.U ){
      mstTimeStamp := Cat( mstTimeStamp(63,48), downRecParser.io.data.bits, mstTimeStamp(39,0) )
    } .elsewhen( syncCnt === 6.U ){
      mstTimeStamp := Cat( mstTimeStamp(63,56), downRecParser.io.data.bits, mstTimeStamp(47,0) )
    } .elsewhen( syncCnt === 7.U ){
      mstTimeStamp := Cat( downRecParser.io.data.bits, mstTimeStamp(55,0) )
    } .elsewhen( syncCnt === 8.U ){
      mstSlvDeltaTimeStamp := mstTimeStamp - downTimeStamp
      mstDeltaTimeStamp := Cat( mstDeltaTimeStamp(31, 8), downRecParser.io.data.bits )
    } .elsewhen( syncCnt === 9.U ){
      mstDeltaTimeStamp := Cat( mstDeltaTimeStamp(31,16), downRecParser.io.data.bits, mstDeltaTimeStamp(7,0) )
    } .elsewhen( syncCnt === 10.U ){
      mstDeltaTimeStamp := Cat( mstDeltaTimeStamp(31,24), downRecParser.io.data.bits, mstDeltaTimeStamp(15,0) )
    } .elsewhen( syncCnt === 11.U ){
      mstDeltaTimeStamp := Cat( downRecParser.io.data.bits, mstDeltaTimeStamp(23, 0) )
    } .otherwise{
      assert(false.B, "Wrong Sync SubMsg!\n")
    }
  }

  when( RegNext(isSync) & ~isSync ){
    val deltaMstSlvDeltaTimeStamp_org = mstDeltaTimeStamp - slvDeltaTimeStamp
    deltaMstSlvDeltaTimeStamp := Cat( deltaMstSlvDeltaTimeStamp_org.extract(deltaMstSlvDeltaTimeStamp_org.getWidth-1), deltaMstSlvDeltaTimeStamp_org(deltaMstSlvDeltaTimeStamp_org.getWidth-1, 1) ) //(mstDeltaTimeStamp - slvDeltaTimeStamp) >> 1
  } .elsewhen( RegNext(RegNext(isSync)) & ~RegNext(isSync) ){
    deltaFinal := mstSlvDeltaTimeStamp + deltaMstSlvDeltaTimeStamp
  }


}

trait SlaveParserProbe{ this: SlaveParserBase =>


  // val ProbeRecAim  = 511.U
  val probeRecCnt = RegInit(0.U(9.W))
  val isWatchDogOverflow = probeRecCnt.andR





  // val isReadyToProbe_Pending = RegInit(false.B)

  when( downRecParser.io.frameReq.fire & downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //下行来了一个嗅探包
    isReadyToProbe := true.B
    when( downSendGen.io.stateCurr =/= STATE_IDLE ){
      printf("Error! downSendGen is busy while a Probe-Frame arrival!\n")
    }
  } .elsewhen( upRecParser.io.frameReq.fire & upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //上行来了一个嗅探包
    isReadyToProbe := false.B
  } .elsewhen( isWatchDogOverflow ){
    isReadyToProbe := false.B
  }

  when( downRecParser.io.frameReq.fire & downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //下行来了一个嗅探包
    isAckProbe := true.B
  } .elsewhen( upSendGen.io.frameReq.fire & upSendGen.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //上行发送回复嗅探包
    isAckProbe := false.B
  }



  // val isLastDevice = RegInit(true.B)

  when( upRecParser.io.frameReq.fire & upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //上行来了一个嗅探包
    isLastDevice := false.B
  } .elsewhen( isWatchDogOverflow ){
    isLastDevice := true.B
  }





  when( upRecParser.io.frameReq.fire & upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //上行来了一个嗅探包
    probeRecCnt := 0.U
  } .elsewhen( isWatchDogOverflow ){
    probeRecCnt := 0.U
  } .elsewhen( isReadyToProbe ){
    probeRecCnt := probeRecCnt + 1.U
  }


  when( upRecParser.io.frameReq.fire & upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //上行来了一个嗅探包
    indexOfRightDev := upRecParser.io.frameReq.bits.frameInfo
    when( upRecParser.io.frameReq.bits.frameInfo =/= localDevIndex + 1.U ){ //索引不对
      isDevOnRightModify := true.B
    } .otherwise{
      isDevOnRightModify := false.B
    }
  }






  io.upOut   <> Queue( upSendGen.io.send, 4, true, false )
  io.downIn  <> downRecParser.io.rec

  io.downOut <> Queue( downSendGen.io.send, 4, true, false )
  io.upIn    <> upRecParser.io.rec

  io.isLoop := isLastDevice & ~isReadyToProbe


  // when( isLastDevice =/= isLastDevice_Pending & ~downSendGen.io.send.valid & ~io.downOut.valid & ~io.upIn.valid ){
  //   isLastDevice := isLastDevice_Pending
  // }

  // when( isReadyToProbe =/= isReadyToProbe_Pending & ~downSendGen.io.send.valid & ~io.downOut.valid & ~io.upIn.valid ){
  //   isReadyToProbe := isReadyToProbe_Pending
  // }
}

class SlaveParser extends SlaveParserBase
with SlaveParserIndex
with SlaveParserRW
with SlaveParserSync
with SlaveParserProbe{
  io.intHWTrig(0) := downRecParser.io.isError
  io.intHWTrig(1) := upRecParser.io.isError

  downRecParser.io.resp := io.intHWClr(0)
  upRecParser.io.resp   := io.intHWClr(1)
}