2025-04-02 16:40:25 +08:00
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package BACK
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import chisel3._
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import chisel3.util._
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2025-04-07 17:39:44 +08:00
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class FrameHeader extends Bundle{
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val frameLenAim = UInt(12.W) //帧长度目标
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val frameStyle = UInt(2.W) //包类型
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}
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class SubMsgHeader extends Bundle{
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val subMsg_devIndex = UInt(14.W) // 子报文中设备索引
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val subMsg_style = UInt(2.W) // 子报文类型
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val subMsg_address = UInt(16.W) //子报文地址
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val subMsg_operator = UInt(4.W) //子报文命令类型
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val subMsg_length = UInt(12.W) //子报文负载长度
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val subMsg_workCnt = UInt(16.W) //子报文工作计数
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}
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class ShareSRAMIO extends Bundle{
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val addr = Input(UInt(15.W))
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val dataw = Input( UInt(8.W) )
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val datar = Output( UInt(8.W) )
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val enw = Input(Bool())
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val enr = Input(Bool())
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}
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2025-04-02 16:40:25 +08:00
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class SlaveParserIO extends Module{
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2025-04-03 17:49:33 +08:00
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val downIn = Flipped( Decoupled(new AXIS_Bundle(8)) )
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2025-04-07 17:39:44 +08:00
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val downOut = Decoupled(new AXIS_Bundle(8))
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2025-04-02 16:40:25 +08:00
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2025-04-03 17:49:33 +08:00
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val upIn = Flipped( Decoupled(new AXIS_Bundle(8)) )
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2025-04-07 17:39:44 +08:00
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val upOut = Decoupled(new AXIS_Bundle(8))
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2025-04-03 17:49:33 +08:00
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2025-04-07 17:39:44 +08:00
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val sram_r = for( 0 until 2 ) yield { Flipped(new ShareSRAMIO) }
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val sram_w = for( 0 until 2 ) yield { Flipped(new ShareSRAMIO) }
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2025-04-02 16:40:25 +08:00
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}
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abstract class SlaveParserBase extends Module{
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val io: SlaveParserIO = IO(new SlaveParserIO)
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2025-04-07 17:39:44 +08:00
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2025-04-05 09:27:15 +08:00
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val devIndex = Reg(UInt(14.W)) //当前设备索引
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2025-04-07 17:39:44 +08:00
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val downRecParser = Module(new SlaveRecParser)
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val upRecParser = Module(new SlaveRecParser)
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val downSendGen = Module(new SlaveSendGen)
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val upSendGen = Module(new SlaveSendGen)
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val downRecFifo = for( i <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 8)) }
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val upRecFifo = for( i <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 8)) }
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val downSinkSel = Reg(Bool())
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val upSinkSel = Reg(Bool())
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val downFrameInfo = Reg(new FrameHeader)
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val downSubMsgInfo = for( 0 until 2 ) yield { Reg(new SubMsgHeader) }
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val upFrameInfo = Reg(new FrameHeader)
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val upSubMsgInfo = for( 0 until 2 ) yield { Reg(new SubMsgHeader) }
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val isDownSendBusy = downRecParser.io.frameReq.ready
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val isUpSendBusy = upRecParser.io.frameReq.ready
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val isDownSendPend = RegInit(false.B)
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val isUpSendPend = RegInit(false.B)
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//同时到来怎么办
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when( downRecParser.io.frameReq.fire ){
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when(downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE){ //下行来了一个嗅探包
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isUpSendPend := true.B
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downFrameInfo := downRecParser.io.frameReq.bits
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println("Warning! No busy protection!")
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} .elsewhen( downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_COMMON ){ //下行来了一个普通包
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isDownSendPend := true.B
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downFrameInfo := downRecParser.io.frameReq.bits
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println("Warning! No busy protection!")
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}
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} .elsewhen( upRecParser.io.frameReq.fire ){
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when( upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE){ //上行来了一个嗅探包
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println("Probe Resp!")
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} .elsewhen( upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_COMMON ){ //上行来了一个普通包
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isUpSendPend := true.B
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upFrameInfo := upRecParser.io.frameReq.bits
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println("Warning! No busy protection!")
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}
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2025-04-05 09:27:15 +08:00
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}
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2025-04-07 17:39:44 +08:00
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val isDownSendProbe: Bool //下行探针
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val isUpSendProbe: Bool //上行探针
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val probeFrame: FrameHeader //固定化探针内容
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downSendGen.io.frameReq.valid :=
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isDownSendPend | isDownSendProbe //下行转发 | 下行探针
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assert( OneHot(isDownSendPend, isDownSendProbe) )
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downSendGen.io.frameReq.bits := Mux1H(Seq(
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isDownSendPend -> downFrameInfo, //下行转发
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isDownSendProbe -> probeFrame, //下行探针
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))
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when( downSendGen.io.frameReq.fire ){
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isDownSendPend := false.B
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2025-04-05 09:27:15 +08:00
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}
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2025-04-07 17:39:44 +08:00
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upSendGen.io.frameReq.valid :=
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isUpSendPend | isUpSendProbe //上行转发 | 上行探针
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assert( OneHot(isUpSendPend, isUpSendProbe) )
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upSendGen.io.frameReq.bits := Mux1H(Seq(
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isUpSendPend -> upFrameInfo, //上行转发
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isUpSendProbe -> probeFrame, //上行探针
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))
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when( upSendGen.io.frameReq.fire ){
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isUpSendPend := false.B
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2025-04-05 09:27:15 +08:00
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}
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2025-04-07 17:39:44 +08:00
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when( downSendGen.io.frameReq.fire ){
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isDownSendPend := false.B
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2025-04-05 09:27:15 +08:00
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}
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2025-04-03 17:49:33 +08:00
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2025-04-07 17:39:44 +08:00
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upSendFifo.io.enq.bits := Mux1H(Seq(
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( downRecParser.io.frameStyle === FRAME_STYLE_PROBE & downRecParser.io.stateCurr > STATE_HEADER ) -> downRecParser.io.data.bits //嗅探包 bypass到上行
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))
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upSendFifo.io.enq.valid :=
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((downRecParser.io.frameStyle === FRAME_STYLE_PROBE & downRecParser.io.stateCurr > STATE_HEADER ) & downRecParser.io.data.valid) |
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downRecParser.io.data.ready :=
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((downRecParser.io.frameStyle === FRAME_STYLE_PROBE & downRecParser.io.stateCurr > STATE_HEADER ) & upSendFifo.io.enq.ready ) |
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downSendFifo.io.enq.bits := Mux1H(Seq(
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( downRecParser.io.frameStyle === FRAME_STYLE_COMMON & downRecParser.io.stateCurr > STATE_HEADER ) ->
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))
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val isDownIdle
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val isDownBypassToDown
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val isDownWriteToSRAM
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val isDownReadFromSRAM
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val isDownLoopBack
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val isUpIdle
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val isUpBypassToUp
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val isUpWriteToSRAM
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val isUpReadFromSRAM
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val isUpBlackHole
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// val downOutFifo = Module(new Queue(UInt(8.W), 8))
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val upInFifo = Module(new Queue(UInt(8.W), 8))
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// val upOutFifo = Module(new Queue(UInt(8.W), 8))
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downInFifo.io.enq <> io.downIn
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io.downOut.valid :=
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( === FRAME_STYLE_COMMON ) &
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io.upOut.valid :=
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( === FRAME_STYLE_PROBE) & |
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io.upOut.bits :=
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Mux1H(Seq(
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( === FRAME_STYLE_PROBE) -> downInFifo.io.deq.bits, //嗅探包情形
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-> upInFifo.io.deq.bits, //上行
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-> //上行修正数据
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))
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io.downOut.bits :=
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Mux1H(Seq(
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2025-04-07 17:39:44 +08:00
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-> //自主发送嗅探包
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( ) -> downInFifo.io.deq.bits, //下行
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( ) -> //下行修正数据
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2025-04-03 17:49:33 +08:00
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))
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2025-04-07 17:39:44 +08:00
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downInFifo.io.deq.ready :=
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upInFifo.io.deq.ready :=
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2025-04-03 17:49:33 +08:00
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2025-04-02 16:40:25 +08:00
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}
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2025-04-03 17:49:33 +08:00
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2025-04-02 16:40:25 +08:00
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class SlaveParser extends SlaveParserBase{
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}
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