Files
eb001/src/main/scala/backBoard/shin/SlaveParser.scala

264 lines
5.8 KiB
Scala
Raw Normal View History

2025-04-02 16:40:25 +08:00
package BACK
import chisel3._
import chisel3.util._
2025-04-07 17:39:44 +08:00
class FrameHeader extends Bundle{
val frameLenAim = UInt(12.W) //帧长度目标
val frameStyle = UInt(2.W) //包类型
}
class SubMsgHeader extends Bundle{
val subMsg_devIndex = UInt(14.W) // 子报文中设备索引
val subMsg_style = UInt(2.W) // 子报文类型
val subMsg_address = UInt(16.W) //子报文地址
val subMsg_operator = UInt(4.W) //子报文命令类型
val subMsg_length = UInt(12.W) //子报文负载长度
val subMsg_workCnt = UInt(16.W) //子报文工作计数
}
class ShareSRAMIO extends Bundle{
val addr = Input(UInt(15.W))
val dataw = Input( UInt(8.W) )
val datar = Output( UInt(8.W) )
val enw = Input(Bool())
val enr = Input(Bool())
}
2025-04-02 16:40:25 +08:00
class SlaveParserIO extends Module{
2025-04-03 17:49:33 +08:00
val downIn = Flipped( Decoupled(new AXIS_Bundle(8)) )
2025-04-07 17:39:44 +08:00
val downOut = Decoupled(new AXIS_Bundle(8))
2025-04-02 16:40:25 +08:00
2025-04-03 17:49:33 +08:00
val upIn = Flipped( Decoupled(new AXIS_Bundle(8)) )
2025-04-07 17:39:44 +08:00
val upOut = Decoupled(new AXIS_Bundle(8))
2025-04-03 17:49:33 +08:00
2025-04-07 17:39:44 +08:00
val sram_r = for( 0 until 2 ) yield { Flipped(new ShareSRAMIO) }
val sram_w = for( 0 until 2 ) yield { Flipped(new ShareSRAMIO) }
2025-04-02 16:40:25 +08:00
}
abstract class SlaveParserBase extends Module{
val io: SlaveParserIO = IO(new SlaveParserIO)
2025-04-07 17:39:44 +08:00
2025-04-05 09:27:15 +08:00
val devIndex = Reg(UInt(14.W)) //当前设备索引
2025-04-07 17:39:44 +08:00
val downRecParser = Module(new SlaveRecParser)
val upRecParser = Module(new SlaveRecParser)
val downSendGen = Module(new SlaveSendGen)
val upSendGen = Module(new SlaveSendGen)
val downRecFifo = for( i <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 8)) }
val upRecFifo = for( i <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 8)) }
val downSinkSel = Reg(Bool())
val upSinkSel = Reg(Bool())
val downFrameInfo = Reg(new FrameHeader)
val downSubMsgInfo = for( 0 until 2 ) yield { Reg(new SubMsgHeader) }
val upFrameInfo = Reg(new FrameHeader)
val upSubMsgInfo = for( 0 until 2 ) yield { Reg(new SubMsgHeader) }
val isDownSendBusy = downRecParser.io.frameReq.ready
val isUpSendBusy = upRecParser.io.frameReq.ready
val isDownSendPend = RegInit(false.B)
val isUpSendPend = RegInit(false.B)
//同时到来怎么办
when( downRecParser.io.frameReq.fire ){
when(downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE){ //下行来了一个嗅探包
isUpSendPend := true.B
downFrameInfo := downRecParser.io.frameReq.bits
println("Warning! No busy protection!")
} .elsewhen( downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_COMMON ){ //下行来了一个普通包
isDownSendPend := true.B
downFrameInfo := downRecParser.io.frameReq.bits
println("Warning! No busy protection!")
}
} .elsewhen( upRecParser.io.frameReq.fire ){
when( upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE){ //上行来了一个嗅探包
println("Probe Resp!")
} .elsewhen( upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_COMMON ){ //上行来了一个普通包
isUpSendPend := true.B
upFrameInfo := upRecParser.io.frameReq.bits
println("Warning! No busy protection!")
}
2025-04-05 09:27:15 +08:00
}
2025-04-07 17:39:44 +08:00
val isDownSendProbe: Bool //下行探针
val isUpSendProbe: Bool //上行探针
val probeFrame: FrameHeader //固定化探针内容
downSendGen.io.frameReq.valid :=
isDownSendPend | isDownSendProbe //下行转发 | 下行探针
assert( OneHot(isDownSendPend, isDownSendProbe) )
downSendGen.io.frameReq.bits := Mux1H(Seq(
isDownSendPend -> downFrameInfo, //下行转发
isDownSendProbe -> probeFrame, //下行探针
))
when( downSendGen.io.frameReq.fire ){
isDownSendPend := false.B
2025-04-05 09:27:15 +08:00
}
2025-04-07 17:39:44 +08:00
upSendGen.io.frameReq.valid :=
isUpSendPend | isUpSendProbe //上行转发 | 上行探针
assert( OneHot(isUpSendPend, isUpSendProbe) )
upSendGen.io.frameReq.bits := Mux1H(Seq(
isUpSendPend -> upFrameInfo, //上行转发
isUpSendProbe -> probeFrame, //上行探针
))
when( upSendGen.io.frameReq.fire ){
isUpSendPend := false.B
2025-04-05 09:27:15 +08:00
}
2025-04-07 17:39:44 +08:00
when( downSendGen.io.frameReq.fire ){
isDownSendPend := false.B
2025-04-05 09:27:15 +08:00
}
2025-04-03 17:49:33 +08:00
2025-04-07 17:39:44 +08:00
upSendFifo.io.enq.bits := Mux1H(Seq(
( downRecParser.io.frameStyle === FRAME_STYLE_PROBE & downRecParser.io.stateCurr > STATE_HEADER ) -> downRecParser.io.data.bits //嗅探包 bypass到上行
))
upSendFifo.io.enq.valid :=
((downRecParser.io.frameStyle === FRAME_STYLE_PROBE & downRecParser.io.stateCurr > STATE_HEADER ) & downRecParser.io.data.valid) |
downRecParser.io.data.ready :=
((downRecParser.io.frameStyle === FRAME_STYLE_PROBE & downRecParser.io.stateCurr > STATE_HEADER ) & upSendFifo.io.enq.ready ) |
downSendFifo.io.enq.bits := Mux1H(Seq(
( downRecParser.io.frameStyle === FRAME_STYLE_COMMON & downRecParser.io.stateCurr > STATE_HEADER ) ->
))
val isDownIdle
val isDownBypassToDown
val isDownWriteToSRAM
val isDownReadFromSRAM
val isDownLoopBack
val isUpIdle
val isUpBypassToUp
val isUpWriteToSRAM
val isUpReadFromSRAM
val isUpBlackHole
// val downOutFifo = Module(new Queue(UInt(8.W), 8))
val upInFifo = Module(new Queue(UInt(8.W), 8))
// val upOutFifo = Module(new Queue(UInt(8.W), 8))
downInFifo.io.enq <> io.downIn
io.downOut.valid :=
( === FRAME_STYLE_COMMON ) &
io.upOut.valid :=
( === FRAME_STYLE_PROBE) & |
io.upOut.bits :=
Mux1H(Seq(
( === FRAME_STYLE_PROBE) -> downInFifo.io.deq.bits, //嗅探包情形
-> upInFifo.io.deq.bits, //上行
-> //上行修正数据
))
io.downOut.bits :=
2025-04-03 17:49:33 +08:00
Mux1H(Seq(
2025-04-07 17:39:44 +08:00
-> //自主发送嗅探包
( ) -> downInFifo.io.deq.bits, //下行
( ) -> //下行修正数据
2025-04-03 17:49:33 +08:00
))
2025-04-07 17:39:44 +08:00
downInFifo.io.deq.ready :=
upInFifo.io.deq.ready :=
2025-04-03 17:49:33 +08:00
2025-04-02 16:40:25 +08:00
}
2025-04-03 17:49:33 +08:00
2025-04-02 16:40:25 +08:00
class SlaveParser extends SlaveParserBase{
}