eb001/src/main/scala/backBoard/shin/SlaveParser.scala

package BACK

import chisel3._
import chisel3.util._


class FrameHeader extends Bundle{
  val frameLenAim  = UInt(12.W) //帧长度目标
  val frameStyle   = UInt(2.W)  //包类型
  val frameInfo    = UInt(16.W) //其它信息，如probe
}

class SubMsgHeader extends Bundle{
  val devIndex = UInt(14.W) // 子报文中设备索引
  val style    = UInt(2.W)  // 子报文类型
  val address  = UInt(16.W) //子报文地址
  val operator = UInt(4.W)  //子报文命令类型
  val length   = UInt(12.W) //子报文负载长度
  val workCnt  = UInt(16.W) //子报文工作计数
}



// class ShareSRAMIO extends Bundle{
//   val addr  = Input(UInt(15.W))
//   val dataw  = Input( UInt(8.W) )
//   val datar  = Output( UInt(8.W) )
//   val enw    = Input(Bool())
//   val enr    = Input(Bool())
// }



class SlaveParserIO extends Bundle{
  val downIn  = Flipped( Decoupled(new AXIS_Bundle(8)) )
  val downOut = Decoupled(new AXIS_Bundle(8))

  val upIn  = Flipped( Decoupled(new AXIS_Bundle(8)) )
  val upOut = Decoupled(new AXIS_Bundle(8))

  val sram_w = Vec( 4, Flipped(new SRAM2kWRIO))
  val sram_r = Vec( 4, Flipped(new SRAM2kRDIO))

  val dSMenq = Output( Vec(4, Bool()) )
  val uSMdeq = Output( Vec(4, Bool()) )

  val trigAddr = Input( Vec(8, UInt(15.W)) )

  val timeStamp = Input(UInt(64.W))
}

abstract class SlaveParserBase extends Module{
  val io: SlaveParserIO = IO(new SlaveParserIO)



  val FRAME_STYLE_COMMON = 0.U
  val FRAME_STYLE_PROBE  = 1.U

  val STATE_IDLE                = 0.U //空闲
  val STATE_HEADER              = 1.U //长度/ /保留2bits //包类型
  val STATE_PAYLOAD_INDEX_STYLE = 2.U //子报文设备索引 //子报文类型
  val STATE_PAYLOAD_ADDR        = 3.U //子报文地址
  val STATE_PAYLOAD_OP_LENGTH   = 4.U //子报文命令类型 //子报文长度
  val STATE_PAYLOAD_WORKCNT     = 5.U //子报文工作计数
  val STATE_PAYLOAD_DATA        = 6.U //子报文数据
  val STATE_CRC                 = 7.U //CRC校验
  val STATE_ERROR               = 8.U //
  val STATE_WAIT                = 9.U




  val downRecParser = Module(new SlaveRecParser)
  val upRecParser   = Module(new SlaveRecParser)
  val downSendGen = Module(new SlaveSendGen)
  val upSendGen   = Module(new SlaveSendGen)


  val localDevIndex = RegInit(0.U(14.W)) //当前设备索引
  dontTouch(localDevIndex)



  // 认为只有下行到下行，上行到上行模式，探针是独立发起操作
  // val downSinkSel = Reg(Bool())
  // val upSinkSel = Reg(Bool())

  val downFrameInfo  = Reg(new FrameHeader) //下行大包头
  val upFrameInfo  = Reg(new FrameHeader) //上行大包头

  // val isDownSendBusy = downSendGen.io.frameReq.ready
  // val isUpSendBusy   =   upSendGen.io.frameReq.ready

  val isDownSendPend = RegInit(false.B)
  val isUpSendPend = RegInit(false.B)

  // val isUpProbePending

  //处理主报文

  when( downSendGen.io.frameReq.fire ){
    isDownSendPend := false.B
  } .elsewhen( downRecParser.io.frameReq.fire & downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_COMMON ){//下行来了一个普通包
    isDownSendPend := true.B
    downFrameInfo := downRecParser.io.frameReq.bits
  }

  when( upSendGen.io.frameReq.fire ){
    isUpSendPend := false.B
  } .elsewhen( upRecParser.io.frameReq.fire & upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_COMMON ){ //上行来了一个普通包
    isUpSendPend := true.B
    upFrameInfo := upRecParser.io.frameReq.bits
  }




  // val isDownSendProbe: Bool //下行探针
  // val isUpSendProbe: Bool   //上行探针
  // val probeFrame: FrameHeader //固定化探针内容

  downSendGen.io.frameReq.valid :=
    isDownSendPend & downRecParser.io.subMsgReq.fire //| 下行转发
    //isDownSendProbe  //下行探针

  // assert( OneHot(isDownSendPend, isDownSendProbe) )

  downSendGen.io.frameReq.bits  := Mux1H(Seq(
    isDownSendPend -> downFrameInfo,  //下行转发
    //isDownSendProbe -> probeFrame, //下行探针
  ))
  

  val upFrameProbeInfo: FrameHeader = Wire(new FrameHeader)
  upFrameProbeInfo.frameLenAim := 0.U                //帧长度目标
  upFrameProbeInfo.frameStyle  := FRAME_STYLE_PROBE  //包类型
  upFrameProbeInfo.frameInfo   := localDevIndex      //其它信息，如probe

  upSendGen.io.frameReq.valid :=
    isUpSendPend & upRecParser.io.subMsgReq.fire |     //上行转发
    isReadyToProbe // 上行探针

  assert( ~(isUpSendPend & isUpSendProbe), "Assert Failed, Check Softwave, Probe is Sent while transfering!\n" )

  upSendGen.io.frameReq.bits := Mux1H(Seq(
    isUpSendPend   -> upFrameInfo,      //上行转发
    isReadyToProbe -> upFrameProbeInfo, //上行探针
  ))







////////////////////////////////////////

  //子报文
  val isDownSubMsgValid = for( _ <- 0 until 2 ) yield { RegInit(false.B) }
  val isUpSubMsgValid   = for( _ <- 0 until 2 ) yield { RegInit(false.B) }





  //接收子报文

  val downSubMsgInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTxInfo) } //子报文头
  val upSubMsgInfo   = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTxInfo) }



  val downRecFifo = for( _ <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 16)) } //子报文负载
  val upRecFifo   = for( _ <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 16)) }

  val isDownRecPing = RegInit(false.B)
  val isUpRecPing   = RegInit(false.B)



  //下行接收
  when( downRecParser.io.subMsgReq.fire ){
    when( isDownRecPing ){
      downSubMsgInfo(0).devIndex := downRecParser.io.subMsgReq.bits.devIndex
      downSubMsgInfo(0).style    := downRecParser.io.subMsgReq.bits.style
      downSubMsgInfo(0).address  := downRecParser.io.subMsgReq.bits.address
      downSubMsgInfo(0).operator := downRecParser.io.subMsgReq.bits.operator
      downSubMsgInfo(0).length   := downRecParser.io.subMsgReq.bits.length
      downSubMsgInfo(0).workCnt  := downRecParser.io.subMsgReq.bits.workCnt
      downSubMsgInfo(0).source := 0.U
    } .otherwise{ //pong
      downSubMsgInfo(1).devIndex := downRecParser.io.subMsgReq.bits.devIndex
      downSubMsgInfo(1).style    := downRecParser.io.subMsgReq.bits.style
      downSubMsgInfo(1).address  := downRecParser.io.subMsgReq.bits.address
      downSubMsgInfo(1).operator := downRecParser.io.subMsgReq.bits.operator
      downSubMsgInfo(1).length   := downRecParser.io.subMsgReq.bits.length
      downSubMsgInfo(1).workCnt  := downRecParser.io.subMsgReq.bits.workCnt
      downSubMsgInfo(1).source   := 1.U
    }
  }




  when( ~isDownRecPing ){ //req fire 后 已经反相
    downRecFifo(0).io.enq.valid := downRecParser.io.data.valid
    downRecFifo(0).io.enq.bits  := downRecParser.io.data.bits
    downRecParser.io.data.ready := downRecFifo(0).io.enq.ready

    downRecFifo(1).io.enq.valid := false.B
    downRecFifo(1).io.enq.bits  := 0.U

  } .otherwise{
    downRecFifo(0).io.enq.valid := false.B
    downRecFifo(0).io.enq.bits  := 0.U

    downRecFifo(1).io.enq.valid := downRecParser.io.data.valid
    downRecFifo(1).io.enq.bits  := downRecParser.io.data.bits
    downRecParser.io.data.ready := downRecFifo(1).io.enq.ready
  }





  //上行接收
  when( upRecParser.io.subMsgReq.fire ){
    when( isUpRecPing ){
      upSubMsgInfo(0).devIndex := upRecParser.io.subMsgReq.bits.devIndex
      upSubMsgInfo(0).style    := upRecParser.io.subMsgReq.bits.style
      upSubMsgInfo(0).address  := upRecParser.io.subMsgReq.bits.address
      upSubMsgInfo(0).operator := upRecParser.io.subMsgReq.bits.operator
      upSubMsgInfo(0).length   := upRecParser.io.subMsgReq.bits.length
      upSubMsgInfo(0).workCnt  := upRecParser.io.subMsgReq.bits.workCnt
      upSubMsgInfo(0).source := 0.U
    } .otherwise{
      upSubMsgInfo(1).devIndex := upRecParser.io.subMsgReq.bits.devIndex
      upSubMsgInfo(1).style    := upRecParser.io.subMsgReq.bits.style
      upSubMsgInfo(1).address  := upRecParser.io.subMsgReq.bits.address
      upSubMsgInfo(1).operator := upRecParser.io.subMsgReq.bits.operator
      upSubMsgInfo(1).length   := upRecParser.io.subMsgReq.bits.length
      upSubMsgInfo(1).workCnt  := upRecParser.io.subMsgReq.bits.workCnt
      upSubMsgInfo(1).source := 1.U
    }
  }








  //子报文下行发送

  val isDownSendPing = RegInit(false.B)
  val isUpSendPing   = RegInit(false.B)



  downSendGen.io.subMsgReq.valid := 
    ( isDownSendPing & isDownSubMsgValid(0) ) | (~isDownSendPing & isDownSubMsgValid(1))

  downSendGen.io.subMsgReq.bits := Mux( isDownSendPing, downSubMsgInfo(0), downSubMsgInfo(1) )

  when( downSendGen.io.subMsgReq.fire ){ //ready
    isDownSendPing := ~isDownSendPing
    when( isDownSendPing ){
      assert( isDownSubMsgValid(0) )
      isDownSubMsgValid(0) := false.B
    } .otherwise{
      assert( isDownSubMsgValid(1) )
      isDownSubMsgValid(1) := false.B
    }
  } .elsewhen( downRecParser.io.subMsgReq.fire ){
    isDownRecPing := ~isDownRecPing
    when( isDownRecPing ){
      assert( ~isDownSubMsgValid(0) )
      isDownSubMsgValid(0) := true.B
    } .otherwise{
      assert( ~isDownSubMsgValid(1) )
      isDownSubMsgValid(1) := true.B
    }
  }


  downRecFifo(0).io.deq <> downSendGen.io.data(0)
  downRecFifo(1).io.deq <> downSendGen.io.data(1)

  downRecParser.io.resp := ( downRecParser.io.stateCurr === STATE_WAIT ) & (~isDownSubMsgValid(0) & ~isDownSubMsgValid(1))


  //子报文上行发送


  upSendGen.io.subMsgReq.valid := 
    (  isUpSendPing & isUpSubMsgValid(0) ) |
    ( ~isUpSendPing & isUpSubMsgValid(1) )

  upSendGen.io.subMsgReq.bits := Mux( isUpSendPing, upSubMsgInfo(0), upSubMsgInfo(1) )
  
  when( upSendGen.io.subMsgReq.fire ){ //ready
    isUpSendPing := ~isUpSendPing
    when( isUpSendPing ){
      assert( isUpSubMsgValid(0) )
      isUpSubMsgValid(0) := false.B
    } .otherwise{
      assert( isUpSubMsgValid(1) )
      isUpSubMsgValid(1) := false.B
    }
  }.elsewhen( upRecParser.io.subMsgReq.fire ){
    isUpRecPing := ~isUpRecPing
    when( isUpRecPing ){
      assert( ~isUpSubMsgValid(0) )
      isUpSubMsgValid(0) := true.B
    } .otherwise{
      assert( ~isUpSubMsgValid(1) )
      isUpSubMsgValid(1) := true.B
    }
  }

  upRecFifo(0).io.deq <> upSendGen.io.data(0)
  upRecFifo(1).io.deq <> upSendGen.io.data(1)

  upRecParser.io.resp := ( upRecParser.io.stateCurr === STATE_WAIT ) & (~isUpSubMsgValid(0) & ~isUpSubMsgValid(1))

}















trait SlaveParserIndex{ this: SlaveParserBase =>
 //下行接收
  when( downRecParser.io.subMsgReq.fire &
        downRecParser.io.subMsgReq.bits.devIndex === 0.U &
        downRecParser.io.subMsgReq.bits.style === 0.U &
        downRecParser.io.subMsgReq.bits.operator === "hd".U ){ //设置顺序地址
    localDevIndex := downRecParser.io.subMsgReq.bits.workCnt + 1.U
    isDeviceModified := false.B
    when( isDownRecPing ){
      downSubMsgInfo(0).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U
    } .otherwise{ //pong
      downSubMsgInfo(1).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U
    }
  }
}





trait SlaveParserRW{ this: SlaveParserBase =>





  //下行接收
  when( downRecParser.io.subMsgReq.fire ){
    when( isDownRecPing ){
      //override
      when( downRecParser.io.subMsgReq.bits.devIndex === localDevIndex & ( (downRecParser.io.subMsgReq.bits.operator === 1.U) | (downRecParser.io.subMsgReq.bits.operator === 3.U) ) ) { //自身包//写操作或读写操作)
        downSubMsgInfo(0).workCnt  := downRecParser.io.subMsgReq.bits.workCnt + 1.U
      }

    } .otherwise{ //pong
      //override
      when( downRecParser.io.subMsgReq.bits.devIndex === localDevIndex & ( (downRecParser.io.subMsgReq.bits.operator === 1.U) | (downRecParser.io.subMsgReq.bits.operator === 3.U) )) { //自身包//写操作或读写操作 )
        downSubMsgInfo(1).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U
      }
    }
  }



  //写入 SM或寄存器空间

  val addrw = Reg(UInt(15.W))

  val isWRRegister = (addrw(14,11) === "b0000".U)
  val isWRSM0      = (addrw(14,11) === "b0001".U)
  val isWRSM2      = (addrw(14,11) === "b0011".U)
  val isWRSM4      = (addrw(14,11) === "b0101".U)
  val isWRSM6      = (addrw(14,11) === "b0111".U)



  when( downRecParser.io.subMsgReq.fire ){
    when( downRecParser.io.subMsgReq.bits.devIndex === localDevIndex ){
      addrw := downRecParser.io.subMsgReq.bits.address
    }
  }

  val isWrite = (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相
    ( ~isDownRecPing & (downSubMsgInfo(0).devIndex === localDevIndex) & ( (downSubMsgInfo(0).operator === 1.U) | (downSubMsgInfo(0).operator === 3.U) )) |
    (  isDownRecPing & (downSubMsgInfo(1).devIndex === localDevIndex) & ( (downSubMsgInfo(1).operator === 1.U) | (downSubMsgInfo(1).operator === 3.U) ))
  )



  io.sram_w(0).enw   := isWrite & isWRSM0
  io.sram_w(0).addrw := addrw(10,0)
  io.sram_w(0).dataw := downRecParser.io.data.bits

  io.sram_w(1).enw   := isWrite & isWRSM2
  io.sram_w(1).addrw := addrw(10,0)
  io.sram_w(1).dataw := downRecParser.io.data.bits

  io.sram_w(2).enw   := isWrite & isWRSM4
  io.sram_w(2).addrw := addrw(10,0)
  io.sram_w(2).dataw := downRecParser.io.data.bits

  io.sram_w(3).enw   := isWrite & isWRSM6
  io.sram_w(3).addrw := addrw(10,0)
  io.sram_w(3).dataw := downRecParser.io.data.bits


  
  io.dSMenq(0) := isWrite & isWRSM0 & io.trigAddr(0) === addrw(10,0)
  io.uSMdeq(1) := isRead  & isRDSM1 & io.trigAddr(1) === readSMAddr(10,0)
  io.dSMenq(2) := isWrite & isWRSM2 & io.trigAddr(2) === addrw(10,0)
  io.uSMdeq(3) := isRead  & isRDSM3 & io.trigAddr(3) === readSMAddr(10,0)
  io.dSMenq(4) := isWrite & isWRSM4 & io.trigAddr(4) === addrw(10,0)
  io.uSMdeq(5) := isRead  & isRDSM5 & io.trigAddr(5) === readSMAddr(10,0)
  io.dSMenq(6) := isWrite & isWRSM6 & io.trigAddr(6) === addrw(10,0)
  io.uSMdeq(7) := isRead  & isRDSM7 & io.trigAddr(7) === readSMAddr(10,0)




  //上行接收
  when( upRecParser.io.subMsgReq.fire ){
    when( isUpRecPing ){
      //override
      when( upRecParser.io.subMsgReq.bits.devIndex === localDevIndex & ( (upRecParser.io.subMsgReq.bits.operator === 2.U) || (upRecParser.io.subMsgReq.bits.operator === 3.U) ) ){ //自身包//读或读写
        upSubMsgInfo(0).workCnt  := upRecParser.io.subMsgReq.bits.workCnt + 1.U
      }
    } .otherwise{
      //override
      when( upRecParser.io.subMsgReq.bits.devIndex === localDevIndex & ( (upRecParser.io.subMsgReq.bits.operator === 2.U) || (upRecParser.io.subMsgReq.bits.operator === 3.U) )){ //自身包//读或读写 )
        upSubMsgInfo(1).workCnt  := upRecParser.io.subMsgReq.bits.workCnt + 1.U
      }
    }
  }






  //读出uSM  
  val isRead = 
    ((upRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & (upSubMsgInfo(0).devIndex === localDevIndex) & (upSubMsgInfo(0).operator === 2.U | upSubMsgInfo(0).operator === 3.U)) |
    ((upRecParser.io.stateNext === STATE_PAYLOAD_DATA) & (upRecParser.io.subMsgReq.bits.devIndex === localDevIndex) & (upRecParser.io.subMsgReq.bits.operator === 2.U | upRecParser.io.subMsgReq.bits.operator === 3.U))

  val addrr = Reg(UInt(15.W))  
  val readSMAddr = Mux1H(Seq(
    ( upRecParser.io.stateCurr === STATE_PAYLOAD_WORKCNT ) -> upRecParser.io.subMsgReq.bits.address,
    ( upRecParser.io.stateCurr === STATE_PAYLOAD_DATA    ) -> addrr,
  ))

  val isRDRegister = (readSMAddr(14,11) === "b0000".U)
  val isRDSM1      = (readSMAddr(14,11) === "b0010".U)
  val isRDSM3      = (readSMAddr(14,11) === "b0100".U)
  val isRDSM5      = (readSMAddr(14,11) === "b0110".U)
  val isRDSM7      = (readSMAddr(14,11) === "b1000".U)

  when( upRecParser.io.subMsgReq.fire & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex ){
    addrr := upRecParser.io.subMsgReq.bits.address
  }

  val upStreamData = Mux1H(Seq(
    isRDRegister -> 0.U,
    isRDSM1      -> io.sram_r(0).datar,
    isRDSM3      -> io.sram_r(1).datar,
    isRDSM5      -> io.sram_r(2).datar,
    isRDSM7      -> io.sram_r(3).datar,
  ))

  when( ~isUpRecPing ){ //req fire 后 已经反相
    upRecFifo(0).io.enq.valid := upRecParser.io.data.valid
    upRecFifo(0).io.enq.bits  := 
      Mux( upSubMsgInfo(0).devIndex === localDevIndex & (upSubMsgInfo(0).operator === 2.U | upSubMsgInfo(0).operator === 3.U),
        upStreamData, upRecParser.io.data.bits)
    upRecParser.io.data.ready := upRecFifo(0).io.enq.ready

    upRecFifo(1).io.enq.valid := false.B
    upRecFifo(1).io.enq.bits  := 0.U
  } .otherwise{
    upRecFifo(0).io.enq.valid := false.B
    upRecFifo(0).io.enq.bits  := 0.U

    upRecFifo(1).io.enq.valid := upRecParser.io.data.valid
    upRecFifo(1).io.enq.bits  :=
      Mux( upSubMsgInfo(1).devIndex === localDevIndex & (upSubMsgInfo(1).operator === 2.U | upSubMsgInfo(1).operator === 3.U),
        upStreamData, upRecParser.io.data.bits)
    upRecParser.io.data.ready := upRecFifo(1).io.enq.ready

  }

  io.sram_r(0).enr := isRead & isRDSM1
  io.sram_r(1).enr := isRead & isRDSM3
  io.sram_r(2).enr := isRead & isRDSM5
  io.sram_r(3).enr := isRead & isRDSM7

  io.sram_r(0).addrr := readSMAddr(10,0)
  io.sram_r(1).addrr := readSMAddr(10,0)
  io.sram_r(2).addrr := readSMAddr(10,0)
  io.sram_r(3).addrr := readSMAddr(10,0)
}


trait SlaveParserSync{ this: SlaveParserBase =>
  val downTimeStamp = Reg(UInt(64.W)) //下行本地时间戳寄存器 
  val upTimeStamp   = Reg(UInt(64.W)) //上行本地时间戳寄存器
  val mstTimeStamp  = Reg(UInt(64.W)) //主站时间戳
  val mstDeltaTimeStamp = Reg(UInt(32.W)) //主站时间戳差值
  val slvDeltaTimeStamp = Reg(UInt(32.W)) //从站时间戳差值

  val mstSlvDeltaTimeStamp = Reg(UInt(32.W)) //主发从接时间差(中间变量)
  val deltaMstSlvDeltaTimeStamp = Reg(UInt(32.W)) //主差从差时间差(中间变量)
  val deltaFinal = Reg(UInt(32.W)) //当前时间戳与主站时间差


  val recoTimeStamp = Reg(UInt(64.W)) //时钟补偿寄存器

  // recoTimeStamp = io.timeStamp + deltaFinal
  // recoTimeStamp = io.timeStamp + mstSlvDeltaTimeStamp         + deltaMstSlvDeltaTimeStamp
  // recoTimeStamp = io.timeStamp + mstTimeStamp - downTimeStamp + (mstDeltaTimeStamp - slvDeltaTimeStamp            ) >> 1
  // recoTimeStamp = io.timeStamp + mstTimeStamp - downTimeStamp + (mstDeltaTimeStamp - (upTimeStamp - downTimeStamp)) >> 1


  //更新下行本地时间戳寄存器
  when( downRecParser.io.frameReq.fire ){
    downTimeStamp := io.timeStamp
  }

  //更新上行本地时间戳寄存器
  when( upRecParser.io.frameReq.fire ){
    upTimeStamp := io.timeStamp
    slvDeltaTimeStamp := io.timeStamp - downTimeStamp
  }

  //下行接收
  val isSync = (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相
    ( ~isDownRecPing & downSubMsgInfo(0).devIndex === 0.U & downSubMsgInfo(0).operator === "he".U ) |
    (  isDownRecPing & downSubMsgInfo(1).devIndex === 0.U & downSubMsgInfo(1).operator === "he".U )
  )

  val syncCnt = Reg(UInt(4.W))

  when( isSync ){
    syncCnt := syncCnt + 1.U
  } .otherwise{
    syncCnt := 0.U
  }

  when( isSync ){
    when( syncCnt === 0.U ){
      mstTimeStamp := Cat( downRecParser.io.data.bits, mstTimeStamp(55,0) )
    } .elsewhen( syncCnt === 1.U ){
      mstTimeStamp := Cat( mstTimeStamp(63,56), downRecParser.io.data.bits, mstTimeStamp(47,0) )
    } .elsewhen( syncCnt === 2.U ){
      mstTimeStamp := Cat( mstTimeStamp(63,48), downRecParser.io.data.bits, mstTimeStamp(39,0) )
    } .elsewhen( syncCnt === 3.U ){
      mstTimeStamp := Cat( mstTimeStamp(63,40), downRecParser.io.data.bits, mstTimeStamp(31,0) )
    } .elsewhen( syncCnt === 4.U ){
      mstTimeStamp := Cat( mstTimeStamp(63,32), downRecParser.io.data.bits, mstTimeStamp(23,0) )
    } .elsewhen( syncCnt === 5.U ){
      mstTimeStamp := Cat( mstTimeStamp(63,24), downRecParser.io.data.bits, mstTimeStamp(15,0) )
    } .elsewhen( syncCnt === 6.U ){
      mstTimeStamp := Cat( mstTimeStamp(63,16), downRecParser.io.data.bits, mstTimeStamp(7,0) )
    } .elsewhen( syncCnt === 7.U ){
      mstTimeStamp := Cat( mstTimeStamp(63, 8), downRecParser.io.data.bits )
    } .elsewhen( syncCnt === 8.U ){
      mstSlvDeltaTimeStamp := mstTimeStamp - downTimeStamp
      mstDeltaTimeStamp := Cat( downRecParser.io.data.bits, mstDeltaTimeStamp(23, 0) )
    } .elsewhen( syncCnt === 9.U ){
      mstDeltaTimeStamp := Cat( mstDeltaTimeStamp(31,24), downRecParser.io.data.bits, mstDeltaTimeStamp(15,0) )
    } .elsewhen( syncCnt === 10.U ){
      mstDeltaTimeStamp := Cat( mstDeltaTimeStamp(31,16), downRecParser.io.data.bits, mstDeltaTimeStamp(7,0) )
    } .elsewhen( syncCnt === 11.U ){
      mstDeltaTimeStamp := Cat( mstDeltaTimeStamp(31, 8), downRecParser.io.data.bits )
    } .otherwise{
      assert(false.B, "Wrong Sync SubMsg!\n")
    }
  }

  when( RegNext(isSync) & ~isSync ){
    deltaMstSlvDeltaTimeStamp := (mstDeltaTimeStamp - slvDeltaTimeStamp) >> 1
  } .elsewhen( RegNext(RegNext(isSync)) & ~RegNext(isSync) ){
    deltaFinal := mstSlvDeltaTimeStamp + deltaMstSlvDeltaTimeStamp
  }


}

trait SlaveParserProbe{ this: SlaveParserBase =>


  val ProbeRecAim  = 20000.U
  val probeRecCnt = RegInit(0.U(32.W))
  val isWatchDogOverflow = probeRecCnt  === ProbeRecAim





  val isReadyToProbe = RegInit(false.B)

  when( downRecParser.io.frameReq.fire & downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //下行来了一个嗅探包
    isReadyToProbe := true.B
  } .elsewhen( upRecParser.io.frameReq.fire & upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //上行来了一个嗅探包
    isReadyToProbe := false.B
  } .elsewhen( isWatchDogOverflow ){
    isReadyToProbe := false.B
  }







  val isLastDevice: Bool = RegInit(false.B)
  val isDeviceModified: Bool = RegInit(true.B)

  when( upRecParser.io.frameReq.fire & upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //上行来了一个嗅探包
    probeRecCnt := 0.U
    isLastDevice := false.B
  } .elsewhen( isWatchDogOverflow ){
    probeRecCnt := 0.U
    isLastDevice := true.B
  } .elsewhen( isReadyToProbe ){
    probeRecCnt := probeRecCnt + 1.U
  }


  when( upRecParser.io.frameReq.fire & upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //上行来了一个嗅探包
    when( upRecParser.io.frameReq.bits.frameInfo =/= localDevIndex + 1.U ){ //索引不对
      isDeviceModified := true.B
    }
  }



  io.upOut   <> upSendGen.io.send
  io.downIn  <> downRecParser.io.rec

  when( isLastDevice & ~isReadyToProbe ){    //最后一个设备且不是探测模式
    downSendGen.io.send <> upRecParser.io.rec  //axis短接

    io.downOut.valid := false.B                //对外下级io开路
    io.downOut.bits := 0.U.asTypeOf(new AXIS_Bundle(8))
    io.upIn.ready := false.B

  } .otherwise{

    io.downOut <> downSendGen.io.send
    io.upIn    <> upRecParser.io.rec

  }
}

class SlaveParser extends SlaveParserBase
with SlaveParserIndex
with SlaveParserRW
with SlaveParserSync
with SlaveParserProbe