eb001/src/main/scala/backBoard/shin/SlaveParser.scala

package BACK

import chisel3._
import chisel3.util._


class FrameHeader extends Bundle{
  val frameLenAim  = UInt(12.W) //帧长度目标
  val frameStyle   = UInt(2.W)  //包类型
}

class SubMsgHeader extends Bundle{
  val devIndex = UInt(14.W) // 子报文中设备索引
  val style    = UInt(2.W)  // 子报文类型
  val address  = UInt(16.W) //子报文地址
  val operator = UInt(4.W)  //子报文命令类型
  val length   = UInt(12.W) //子报文负载长度
  val workCnt  = UInt(16.W) //子报文工作计数
}



class ShareSRAMIO extends Bundle{
  val addr  = Input(UInt(15.W))
  val dataw  = Input( UInt(8.W) )
  val datar  = Output( UInt(8.W) )
  val enw    = Input(Bool())
  val enr    = Input(Bool())
}



class SlaveParserIO extends Bundle{
  val downIn  = Flipped( Decoupled(new AXIS_Bundle(8)) )
  val downOut = Decoupled(new AXIS_Bundle(8))

  val upIn  = Flipped( Decoupled(new AXIS_Bundle(8)) )
  val upOut = Decoupled(new AXIS_Bundle(8))

  val sram_r = Flipped(new ShareSRAMIO)
  val sram_w = Flipped(new ShareSRAMIO)
}

abstract class SlaveParserBase extends Module{
  val io: SlaveParserIO = IO(new SlaveParserIO)

  val FRAME_STYLE_COMMON = 0.U
  val FRAME_STYLE_PROBE  = 1.U

  val STATE_IDLE                = 0.U //空闲
  val STATE_HEADER              = 1.U //长度/ /保留2bits //包类型
  val STATE_PAYLOAD_INDEX_STYLE = 2.U //子报文设备索引 //子报文类型
  val STATE_PAYLOAD_ADDR        = 3.U //子报文地址
  val STATE_PAYLOAD_OP_LENGTH   = 4.U //子报文命令类型 //子报文长度
  val STATE_PAYLOAD_WORKCNT     = 5.U //子报文工作计数
  val STATE_PAYLOAD_DATA        = 6.U //子报文数据
  val STATE_CRC                 = 7.U //CRC校验
  val STATE_ERROR               = 8.U //
  val STATE_WAIT                = 9.U




  val downRecParser = Module(new SlaveRecParser)
  val upRecParser   = Module(new SlaveRecParser)
  val downSendGen = Module(new SlaveSendGen)
  val upSendGen   = Module(new SlaveSendGen)


  val localDevIndex = Reg(UInt(14.W)) //当前设备索引


  // 认为只有下行到下行，上行到上行模式，探针是独立发起操作
  // val downSinkSel = Reg(Bool())
  // val upSinkSel = Reg(Bool())

  val downFrameInfo  = Reg(new FrameHeader) //下行大包头

  val upFrameInfo  = Reg(new FrameHeader) //上行大包头

  val isDownSendBusy = downSendGen.io.frameReq.ready
  val isUpSendBusy   =   upSendGen.io.frameReq.ready

  val isDownSendPend = RegInit(false.B)
  val isUpSendPend = RegInit(false.B)

  // val isUpProbePending

  //处理主报文
    // when(downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE){ //下行来了一个嗅探包
    //   // isUpSendPend := true.B //嗅探包不会立即发送，而是看门狗形式
    //   //downFrameInfo := downRecParser.io.frameReq.bits
    // } .elsewhen(  ){ 


  when( downSendGen.io.frameReq.fire ){
    isDownSendPend := false.B
  } .elsewhen( downRecParser.io.frameReq.fire & downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_COMMON ){//下行来了一个普通包
    isDownSendPend := true.B
    downFrameInfo := downRecParser.io.frameReq.bits
  }

    // when( upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE){ //上行来了一个嗅探包
    //   println("Probe Resp!")

  when( upSendGen.io.frameReq.fire ){
    isUpSendPend := false.B
  } .elsewhen( upRecParser.io.frameReq.fire & upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_COMMON ){ //上行来了一个普通包
    isUpSendPend := true.B
    upFrameInfo := upRecParser.io.frameReq.bits
  }




  // val isDownSendProbe: Bool //下行探针
  // val isUpSendProbe: Bool   //上行探针
  // val probeFrame: FrameHeader //固定化探针内容

  downSendGen.io.frameReq.valid :=
    isDownSendPend //| 下行转发
    //isDownSendProbe  //下行探针

  // assert( OneHot(isDownSendPend, isDownSendProbe) )

  downSendGen.io.frameReq.bits  := Mux1H(Seq(
    isDownSendPend -> downFrameInfo,  //下行转发
    //isDownSendProbe -> probeFrame, //下行探针
  ))
  



  upSendGen.io.frameReq.valid :=
    isUpSendPend //|     上行转发
    //isUpSendProbe |   // 上行探针

  // assert( OneHot(isUpSendPend, isUpSendProbe) )

  upSendGen.io.frameReq.bits := Mux1H(Seq(
    isUpSendPend -> upFrameInfo, //上行转发
    //isUpSendProbe -> probeFrame, //上行探针
  ))







////////////////////////////////////////

  //子报文
  val isDownSubMsgValid = for( _ <- 0 until 2 ) yield { RegInit(false.B) }
  val isUpSubMsgValid   = for( _ <- 0 until 2 ) yield { RegInit(false.B) }





  //接收子报文

  val downSubMsgInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTxInfo) } //子报文头
  val upSubMsgInfo   = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTxInfo) }



  val downRecFifo = for( _ <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 8)) } //子报文负载
  val upRecFifo   = for( _ <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 8)) }

  val isDownRecPing = RegInit(false.B)
  val isUpRecPing   = RegInit(false.B)



  //下行接收
  when( downRecParser.io.subMsgReq.fire ){
    when( isDownRecPing ){
      downSubMsgInfo(0).devIndex := downRecParser.io.subMsgReq.bits.devIndex
      downSubMsgInfo(0).style    := downRecParser.io.subMsgReq.bits.style
      downSubMsgInfo(0).address  := downRecParser.io.subMsgReq.bits.address
      downSubMsgInfo(0).operator := downRecParser.io.subMsgReq.bits.operator
      downSubMsgInfo(0).length   := downRecParser.io.subMsgReq.bits.length
      downSubMsgInfo(0).workCnt  := 
        Mux(
          downRecParser.io.subMsgReq.bits.devIndex === localDevIndex & (//自身包
            (downRecParser.io.subMsgReq.bits.operator === 1.U) | (downRecParser.io.subMsgReq.bits.operator === 3.U) //写操作或读写操作
          ), downRecParser.io.subMsgReq.bits.workCnt + 1.U, downRecParser.io.subMsgReq.bits.workCnt
        )
        
      downSubMsgInfo(0).source := 0.U

    } .otherwise{
      downSubMsgInfo(1).devIndex := downRecParser.io.subMsgReq.bits.devIndex
      downSubMsgInfo(1).style    := downRecParser.io.subMsgReq.bits.style
      downSubMsgInfo(1).address  := downRecParser.io.subMsgReq.bits.address
      downSubMsgInfo(1).operator := downRecParser.io.subMsgReq.bits.operator
      downSubMsgInfo(1).length   := downRecParser.io.subMsgReq.bits.length
      downSubMsgInfo(1).workCnt  := 
        Mux(
          downRecParser.io.subMsgReq.bits.devIndex === localDevIndex & (//自身包
            (downRecParser.io.subMsgReq.bits.operator === 1.U) | (downRecParser.io.subMsgReq.bits.operator === 3.U) //写操作或读写操作
          ), downRecParser.io.subMsgReq.bits.workCnt + 1.U, downRecParser.io.subMsgReq.bits.workCnt
        )
      downSubMsgInfo(1).source := 1.U

    }
  }




  when( isDownRecPing ){
    downRecFifo(0).io.enq.valid := downRecParser.io.data.valid
    downRecFifo(0).io.enq.bits  := downRecParser.io.data.bits
    downRecParser.io.data.ready := downRecFifo(0).io.enq.ready

    downRecFifo(1).io.enq.valid := false.B
    downRecFifo(1).io.enq.bits  := 0.U

  } .otherwise{
    downRecFifo(0).io.enq.valid := false.B
    downRecFifo(0).io.enq.bits  := 0.U

    downRecFifo(1).io.enq.valid := downRecParser.io.data.valid
    downRecFifo(1).io.enq.bits  := downRecParser.io.data.bits
    downRecParser.io.data.ready := downRecFifo(1).io.enq.ready
  }

  //写入sram

  val addrw = Reg(UInt(15.W))

  when( downRecParser.io.subMsgReq.fire ){
    when( downRecParser.io.subMsgReq.bits.devIndex === localDevIndex ){
      addrw := downRecParser.io.subMsgReq.bits.address
    } .otherwise{
      addrw := 0.U //清零方便调试识别
    }
  } .elsewhen( io.sram_w.enw ){
    addrw := addrw + 1.U
  }


  io.sram_w.enr := false.B

  io.sram_w.enw := 
    ( isDownRecPing & downSubMsgInfo(0).devIndex === localDevIndex & (downSubMsgInfo(0).operator === 1.U | downSubMsgInfo(0).operator === 3.U)) |
    (~isDownRecPing & downSubMsgInfo(1).devIndex === localDevIndex & (downSubMsgInfo(1).operator === 1.U | downSubMsgInfo(1).operator === 3.U))
  


  io.sram_w.addr   := addrw
  io.sram_w.dataw   := downRecParser.io.data.bits






  //上行接收
  when( upRecParser.io.subMsgReq.fire ){
    when( isUpRecPing ){
      upSubMsgInfo(0).devIndex := upRecParser.io.subMsgReq.bits.devIndex
      upSubMsgInfo(0).style    := upRecParser.io.subMsgReq.bits.style
      upSubMsgInfo(0).address  := upRecParser.io.subMsgReq.bits.address
      upSubMsgInfo(0).operator := upRecParser.io.subMsgReq.bits.operator
      upSubMsgInfo(0).length   := upRecParser.io.subMsgReq.bits.length
      upSubMsgInfo(0).workCnt  :=
        Mux(
          upRecParser.io.subMsgReq.bits.devIndex === localDevIndex & ( //自身包
            (upRecParser.io.subMsgReq.bits.operator === 2.U) || (upRecParser.io.subMsgReq.bits.operator === 3.U) //读或读写
          ), upRecParser.io.subMsgReq.bits.workCnt + 1.U, upRecParser.io.subMsgReq.bits.workCnt
        )
      upSubMsgInfo(0).source := 0.U
    } .otherwise{
      upSubMsgInfo(1).devIndex := upRecParser.io.subMsgReq.bits.devIndex
      upSubMsgInfo(1).style    := upRecParser.io.subMsgReq.bits.style
      upSubMsgInfo(1).address  := upRecParser.io.subMsgReq.bits.address
      upSubMsgInfo(1).operator := upRecParser.io.subMsgReq.bits.operator
      upSubMsgInfo(1).length   := upRecParser.io.subMsgReq.bits.length
      upSubMsgInfo(1).workCnt  := 
        Mux(
          upRecParser.io.subMsgReq.bits.devIndex === localDevIndex & ( //自身包
            (upRecParser.io.subMsgReq.bits.operator === 2.U) || (upRecParser.io.subMsgReq.bits.operator === 3.U) //读或读写
          ), upRecParser.io.subMsgReq.bits.workCnt + 1.U, upRecParser.io.subMsgReq.bits.workCnt
        )
      upSubMsgInfo(1).source := 1.U

    }
  }

  when( isUpRecPing ){
    upRecFifo(0).io.enq.valid := upRecParser.io.data.valid
    upRecFifo(0).io.enq.bits  := 
      Mux( upSubMsgInfo(0).devIndex === localDevIndex & (upSubMsgInfo(0).operator === 2.U | upSubMsgInfo(0).operator === 3.U),
        io.sram_r.datar, upRecParser.io.data.bits)
    upRecParser.io.data.ready := upRecFifo(0).io.enq.ready

    upRecFifo(1).io.enq.valid := false.B
    upRecFifo(1).io.enq.bits  := 0.U
  } .otherwise{
    upRecFifo(0).io.enq.valid := false.B
    upRecFifo(0).io.enq.bits  := 0.U

    upRecFifo(1).io.enq.valid := upRecParser.io.data.valid
    upRecFifo(1).io.enq.bits  :=
      Mux( upSubMsgInfo(1).devIndex === localDevIndex & (upSubMsgInfo(1).operator === 2.U | upSubMsgInfo(1).operator === 3.U),
        io.sram_r.datar, upRecParser.io.data.bits)
    upRecParser.io.data.ready := upRecFifo(1).io.enq.ready

  }

  //读出SRAM
  val addrr = Reg(UInt(15.W))

  when( upRecParser.io.subMsgReq.fire ){
    when(upRecParser.io.subMsgReq.bits.devIndex === localDevIndex){
      addrr := upRecParser.io.subMsgReq.bits.address
    } .otherwise{
      addrr := 0.U //用于方便调试
    }
  } .elsewhen( io.sram_r.enr ){
    addrr := addrr + 1.U
  }

  io.sram_r.enw   := false.B
  io.sram_r.dataw := 0.U
  io.sram_r.enr := 
    upRecParser.io.stateNext === STATE_PAYLOAD_DATA
    // ( isUpRecPing & upSubMsgInfo(0).devIndex === localDevIndex & (upSubMsgInfo(0).operator === 1.U | upSubMsgInfo(0).operator === 3.U)) |
    // (~isUpRecPing & upSubMsgInfo(1).devIndex === localDevIndex & (upSubMsgInfo(1).operator === 1.U | upSubMsgInfo(1).operator === 3.U))

  io.sram_r.addr := addrr


  //子报文下行发送

  val isDownSendPing = RegInit(false.B)
  val isUpSendPing   = RegInit(false.B)

  val isLastDevice: Bool = false.B

  downSendGen.io.subMsgReq.valid := 
    ( isDownSendPing & isDownSubMsgValid(0) ) | (~isDownSendPing & isDownSubMsgValid(1))

  downSendGen.io.subMsgReq.bits := Mux( isDownSendPing, downSubMsgInfo(0), downSubMsgInfo(1) )

  when( downSendGen.io.subMsgReq.fire ){ //ready
    isDownSendPing := ~isDownSendPing
    when( isDownSendPing ){
      assert( isDownSubMsgValid(0) )
      isDownSubMsgValid(0) := false.B
    } .otherwise{
      assert( isDownSubMsgValid(1) )
      isDownSubMsgValid(1) := false.B
    }
  } .elsewhen( downRecParser.io.subMsgReq.fire ){
    when( isDownRecPing ){
      isDownRecPing := ~isDownRecPing
      assert( ~isDownSubMsgValid(0) )
      isDownSubMsgValid(0) := true.B
    } .otherwise{
      assert( ~isDownSubMsgValid(1) )
      isDownSubMsgValid(1) := true.B
    }
  }


  downRecFifo(0).io.deq <> downSendGen.io.data(0)
  downRecFifo(1).io.deq <> downSendGen.io.data(1)

  downRecParser.io.resp := ( downRecParser.io.stateCurr === STATE_WAIT ) & (~isDownSubMsgValid(0) & ~isDownSubMsgValid(1))


  //子报文上行发送

  upSendGen.io.subMsgReq.valid := 
    ( isUpSendPing & isUpSubMsgValid(0) ) | (~isUpSendPing & isUpSubMsgValid(1))

  upSendGen.io.subMsgReq.bits := Mux( isUpSendPing, upSubMsgInfo(0), upSubMsgInfo(1) )

  when( upSendGen.io.subMsgReq.fire ){ //ready
    isUpSendPing := ~isUpSendPing
    when( isUpSendPing ){
      assert( isUpSubMsgValid(0) )
      isUpSubMsgValid(0) := false.B
    } .otherwise{
      assert( isUpSubMsgValid(1) )
      isUpSubMsgValid(1) := false.B
    }
  }.elsewhen( upRecParser.io.subMsgReq.fire ){
    isUpRecPing := ~isUpRecPing
    when( isUpRecPing ){
      assert( ~isUpSubMsgValid(0) )
      isUpSubMsgValid(0) := true.B
    } .otherwise{
      assert( ~isUpSubMsgValid(1) )
      isUpSubMsgValid(1) := true.B
    }
  }

  upRecFifo(0).io.deq <> upSendGen.io.data(0)
  upRecFifo(1).io.deq <> upSendGen.io.data(1)

  upRecParser.io.resp := ( upRecParser.io.stateCurr === STATE_WAIT ) & (~isUpSubMsgValid(0) & ~isUpSubMsgValid(1))












  val isReadyToProbe = RegInit(false.B)


  io.upOut   <> upSendGen.io.send
  io.downIn  <> downRecParser.io.rec

  when( isLastDevice & isReadyToProbe ){
    downSendGen.io.send <> upRecParser.io.rec

    io.downOut.valid := false.B
    io.downOut.bits := 0.U.asTypeOf(new AXIS_Bundle(8))
    io.upIn.ready := false.B

  } .otherwise{
    
    io.downOut <> downSendGen.io.send
    io.upIn    <> upRecParser.io.rec

  }


class SlaveParser extends SlaveParserBase




























}





class SlaveParser extends SlaveParserBase{

}