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从站编译完成

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This commit is contained in:
Ruige Lee
2025-04-24 17:31:44 +08:00
parent 4013e19eda
commit dc67286e23
8 changed files with 259 additions and 236 deletions
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204
src/main/scala/backBoard/shin/Interface.scala
View File

@@ -1,132 +1,132 @@
package BACK
// package BACK
import chisel3._
import chisel3.util._
// import chisel3._
// import chisel3.util._
class MasterRegisterBundle extends Bundle{
val isMstNSlv = Bool()
val hwVersion = UInt(8.W)
val hwSerial = UInt(48.W)
val busRate = UInt(16.W)
// class MasterRegisterBundle extends Bundle{
// val isMstNSlv = Bool()
// val hwVersion = UInt(8.W)
// val hwSerial = UInt(48.W)
// val busRate = UInt(16.W)
val isExInfoInit = Bool()
val isTxReq = UInt(8.W)
val txStatus = UInt(16.W)
val spiSel = UInt(2.W)
// val isExInfoInit = Bool()
// val isTxReq = UInt(8.W)
// val txStatus = UInt(16.W)
// val spiSel = UInt(2.W)
val isSoftReset = Bool()
val encryptKey = UInt(128.W)
val isEncrypt = Bool()
// val isSoftReset = Bool()
// val encryptKey = UInt(128.W)
// val isEncrypt = Bool()
val intEnable = UInt(8.W)
val intMask = UInt(8.W)
val intStatus = UInt(8.W)
// val intEnable = UInt(8.W)
// val intMask = UInt(8.W)
// val intStatus = UInt(8.W)
val upRecErrorCnt = UInt(32.W)
val downRecErrorCnt = UInt(32.W)
// val upRecErrorCnt = UInt(32.W)
// val downRecErrorCnt = UInt(32.W)
val upForwardErrorCnt = UInt(32.W)
val downForwardErrorCnt = UInt(32.W)
// val upForwardErrorCnt = UInt(32.W)
// val downForwardErrorCnt = UInt(32.W)
val qspiErrorCnt = UInt(32.W)
val forwardCnt = UInt(32.W)
val recByteCnt = UInt(32.W)
val forwardByteCnt = UInt(32.W)
// val qspiErrorCnt = UInt(32.W)
// val forwardCnt = UInt(32.W)
// val recByteCnt = UInt(32.W)
// val forwardByteCnt = UInt(32.W)
val linkStatus = UInt(8.W)
// val linkStatus = UInt(8.W)
val wdtStatus = UInt(16.W)
val wdtOverflow = UInt(8.W)
// val wdtStatus = UInt(16.W)
// val wdtOverflow = UInt(8.W)
val timeStamp = UInt(64.W)
val deltaTime = UInt(32.W)
}
// val timeStamp = UInt(64.W)
// val deltaTime = UInt(32.W)
// }
class SlaveRegisterBundle extends Bundle{
val isMstNSlv = Bool()
val hwVersion = UInt(8.W)
val hwSerial = UInt(48.W)
val busRate = UInt(16.W)
// class SlaveRegisterBundle extends Bundle{
// val isMstNSlv = Bool()
// val hwVersion = UInt(8.W)
// val hwSerial = UInt(48.W)
// val busRate = UInt(16.W)
val RAMSize = UInt(8.W)
val MMUNum = UInt(8.W)
// val RAMSize = UInt(8.W)
// val MMUNum = UInt(8.W)
val nodeSeqAddr = UInt(16.W)
val nodeSetAddr = UInt(16.W)
// val nodeSeqAddr = UInt(16.W)
// val nodeSetAddr = UInt(16.W)
val spiSel = UInt(2.W)
// val spiSel = UInt(2.W)
val isSoftReset = Bool()
val encryptKey = UInt(128.W)
val isEncrypt = Bool()
// val isSoftReset = Bool()
// val encryptKey = UInt(128.W)
// val isEncrypt = Bool()
val ebmmu = Vec(8, new Bundle{
val logicAddr = UInt(32.W)
val length = UInt(16.W)
val phyAddr = UInt(32.W)
val op = UInt(2.W)
val enable = Bool()
})
// val ebmmu = Vec(8, new Bundle{
// val logicAddr = UInt(32.W)
// val length = UInt(16.W)
// val phyAddr = UInt(32.W)
// val op = UInt(2.W)
// val enable = Bool()
// })
val intStatus = UInt(16.W)
val mb = Vec(8, new Bundle{
val ctrl = UInt(8.W)
val status = UInt(8.W)
})
// val intStatus = UInt(16.W)
// val mb = Vec(8, new Bundle{
// val ctrl = UInt(8.W)
// val status = UInt(8.W)
// })
val upRecErrorCnt = UInt(32.W)
val downRecErrorCnt = UInt(32.W)
// val upRecErrorCnt = UInt(32.W)
// val downRecErrorCnt = UInt(32.W)
val upForwardErrorCnt = UInt(32.W)
val downForwardErrorCnt = UInt(32.W)
// val upForwardErrorCnt = UInt(32.W)
// val downForwardErrorCnt = UInt(32.W)
val qspiErrorCnt = UInt(32.W)
val forwardCnt = UInt(32.W)
val recByteCnt = UInt(32.W)
val forwardByteCnt = UInt(32.W)
// val qspiErrorCnt = UInt(32.W)
// val forwardCnt = UInt(32.W)
// val recByteCnt = UInt(32.W)
// val forwardByteCnt = UInt(32.W)
val linkStatus = UInt(8.W)
// val linkStatus = UInt(8.W)
val wdtStatus = UInt(16.W)
val wdtOverflow = UInt(8.W)
// val wdtStatus = UInt(16.W)
// val wdtOverflow = UInt(8.W)
val timeStamp = UInt(64.W)
val downTimeStamp = UInt(64.W) //下行本地时间戳寄存器
val upTimeStamp = UInt(64.W) //上行本地时间戳寄存器
val mstTimeStamp = UInt(64.W) //主站时间戳
val deltaTime = UInt(32.W)
// val timeStamp = UInt(64.W)
// val downTimeStamp = UInt(64.W) //下行本地时间戳寄存器
// val upTimeStamp = UInt(64.W) //上行本地时间戳寄存器
// val mstTimeStamp = UInt(64.W) //主站时间戳
// val deltaTime = UInt(32.W)
val dcSyncEnable = Bool()
val dcSyncWidth = UInt(16.W)
}
// val dcSyncEnable = Bool()
// val dcSyncWidth = UInt(16.W)
// }
class SPIInterfaceIO extends Bundle{
val sck = Input(Bool())
val csn = Input(Bool())
val mosi = Input(Bool())
val miso = Output(Bool())
}
// class SPIInterfaceIO extends Bundle{
// val sck = Input(Bool())
// val csn = Input(Bool())
// val mosi = Input(Bool())
// val miso = Output(Bool())
// }
class InterfaceIO extends Bundle{
val spi = new SPIInterfaceIO
// class InterfaceIO extends Bundle{
// val spi = new SPIInterfaceIO
val req = Valid(new Bundle{
val addr = UInt(16.W)
val dataw = UInt(8.W)
val isWRn = Bool()
})
// val req = Valid(new Bundle{
// val addr = UInt(16.W)
// val dataw = UInt(8.W)
// val isWRn = Bool()
// })
val resp = Valid(new Bundle{
datar = UInt(8.W)
})
}
// val resp = Valid(new Bundle{
// datar = UInt(8.W)
// })
// }
abstract class InterfaceBase extends Module{
val io: InterfaceIO = IO(new InterfaceIO)
// abstract class InterfaceBase extends Module{
// val io: InterfaceIO = IO(new InterfaceIO)
@@ -137,18 +137,18 @@ abstract class InterfaceBase extends Module{
// val softReset = Reg(Bool())
// val logicAddr = Reg(UInt(30.W))
// val logicLength = Reg(UInt(16.W))
// val phyAddr - Reg(UInt(16.W))
// // val softReset = Reg(Bool())
// // val logicAddr = Reg(UInt(30.W))
// // val logicLength = Reg(UInt(16.W))
// // val phyAddr - Reg(UInt(16.W))
}
// }
class Interface extends InterfaceBase{
// class Interface extends InterfaceBase{
}
// }

128
src/main/scala/backBoard/shin/MasterParser.scala
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@@ -1,90 +1,90 @@
package BACK
// package BACK
import chisel3._
import chisel3.util._
// import chisel3._
// import chisel3.util._
class MasterParserIO extends Module{
val downOut = Decoupled(new AXIS_Bundle(8))
val upIn = Flipped( Decoupled(new AXIS_Bundle(8)) )
// class MasterParserIO extends Module{
// val downOut = Decoupled(new AXIS_Bundle(8))
// val upIn = Flipped( Decoupled(new AXIS_Bundle(8)) )
val sram_r = Flipped(new ShareSRAMIO)
val sram_w = Flipped(new ShareSRAMIO)
// val sram_r = Flipped(new ShareSRAMIO)
// val sram_w = Flipped(new ShareSRAMIO)
val req = Valid(new Bundle{
val length = UInt(12.W)
})
val rsp = Valid(new Bundle{
val isError = Bool()
val length = UInt(12.W)
})
// val req = Valid(new Bundle{
// val length = UInt(12.W)
// })
// val rsp = Valid(new Bundle{
// val isError = Bool()
// val length = UInt(12.W)
// })
}
// }
abstract class MasterParserBase extends Module{
val io: MasterParserIO = IO(new MasterParserIO)
// abstract class MasterParserBase extends Module{
// val io: MasterParserIO = IO(new MasterParserIO)
val sendCnt = Reg(UInt(11.W))
val sendLen = Reg(UInt(11.W))
// val sendCnt = Reg(UInt(11.W))
// val sendLen = Reg(UInt(11.W))
val reqReady = RegInit(true.B)
val sendAddr = Reg(UInt(12.W))
// val reqReady = RegInit(true.B)
// val sendAddr = Reg(UInt(12.W))
io.req.ready := reqReady
// io.req.ready := reqReady
when( io.req.fire ){
reqReady := false.B
} .elsewhen( io.downOut.fire & sendCnt === sendLen ){
reqReady := true.B
}
// when( io.req.fire ){
// reqReady := false.B
// } .elsewhen( io.downOut.fire & sendCnt === sendLen ){
// reqReady := true.B
// }
when( io.req.fire ){
sendLen := io.req.bits.length
sendCnt := 0.U
} .elsewhen( io.downOut.fire ){
sendCnt := sendCnt + 1.U
}
// when( io.req.fire ){
// sendLen := io.req.bits.length
// sendCnt := 0.U
// } .elsewhen( io.downOut.fire ){
// sendCnt := sendCnt + 1.U
// }
when( reqReady ){
sendAddr := 0.U
} .elsewhen( io.downOut.fire ){
sendAddr := sendAddr + 1.U
}
// when( reqReady ){
// sendAddr := 0.U
// } .elsewhen( io.downOut.fire ){
// sendAddr := sendAddr + 1.U
// }
io.sram_r.enr :=
io.req.fire | io.downOut.fire
// io.sram_r.enr :=
// io.req.fire | io.downOut.fire
io.sram_r.addr := Mux( io.req.fire, io.req.bits.addr, sendCnt )
// io.sram_r.addr := Mux( io.req.fire, io.req.bits.addr, sendCnt )
io.downOut.valid := ~reqReady
io.downOut.bits.tdata := io.req.bits.datar
io.downOut.bits.tuser := false.B
io.downOut.bits.tlast := sendCnt === sendLen
// io.downOut.valid := ~reqReady
// io.downOut.bits.tdata := io.req.bits.datar
// io.downOut.bits.tuser := false.B
// io.downOut.bits.tlast := sendCnt === sendLen
val recAddr = Reg(UInt(12.W))
// val recAddr = Reg(UInt(12.W))
io.upIn.ready := true.B
// io.upIn.ready := true.B
io.sram_w.enw := io.upIn.fire
io.sram_w.addr := recAddr
io.sram_w.dataw := io.upIn.bits.tdata
// io.sram_w.enw := io.upIn.fire
// io.sram_w.addr := recAddr
// io.sram_w.dataw := io.upIn.bits.tdata
when( io.upIn.fire ){
when( io.upIn.bits.tlast ){
recAddr := 0.U
} .otherwise{
recAddr := recAddr + 1.U
}
}
// when( io.upIn.fire ){
// when( io.upIn.bits.tlast ){
// recAddr := 0.U
// } .otherwise{
// recAddr := recAddr + 1.U
// }
// }
io.rsp.valid := io.upIn.fire & io.upIn.bits.tlast
io.rsp.bits.isError := io.upIn.fire & io.upIn.bits.tuser
io.rsp.bits.length := recAddr
// io.rsp.valid := io.upIn.fire & io.upIn.bits.tlast
// io.rsp.bits.isError := io.upIn.fire & io.upIn.bits.tuser
// io.rsp.bits.length := recAddr
@@ -92,9 +92,9 @@ abstract class MasterParserBase extends Module{
}
// }
class MasterParser extends MasterParserBase{
// class MasterParser extends MasterParserBase{
}
// }

40
src/main/scala/backBoard/shin/SMUnit.scala
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@@ -4,37 +4,33 @@ import chisel3._
import chisel3.util._
// class SRAM2kWRIO extends Bundle {
// val addrw = Output(UInt(11.W))
// val dataw = Output( UInt(8.W) )
// val enw = Output(Bool())
// }
class SRAM2kWRIO extends Bundle {
val addrw = Input(UInt(11.W))
val dataw = Input( UInt(8.W) )
val enw = Input(Bool())
}
// class SRAM2kRDIO extends Bundle {
// val addrr = Output(UInt(11.W))
// val datar = Input( UInt(8.W) )
// val enr = Output(Bool())
// }
class SRAM2kRDIO extends Bundle {
val addrr = Input(UInt(11.W))
val datar = Output( UInt(8.W) )
val enr = Input(Bool())
}
// class SRAM2kIO extends Bundle {
// val addrr = Output(UInt(11.W))
// val addrw = Output(UInt(11.W))
// val dataw = Output( UInt(8.W) )
// val datar = Input( UInt(8.W) )
// val enw = Output(Bool())
// val enr = Output(Bool())
// }
class SRAM2kIO extends Bundle {
val rd = new SRAM2kRDIO
val wr = new SRAM2kWRIO
}
class SMUnitIO(depth: Int) extends Bundle {
val sram_w = Flipped(new SRAM2kWRIO)
val sram_r = Flipped(new SRAM2kRDIO)
val sram_w = new SRAM2kWRIO
val sram_r = new SRAM2kRDIO
val enq = Input(Bool())
val deq = Input(Bool())
val sram = Vec(depth, new SRAM2kIO)
val sram = Flipped(Vec(depth, new SRAM2kIO))
}
@@ -71,7 +67,7 @@ abstract class SMUnitBase(depth: Int = 4) extends Module {
for( i <- 0 until depth ){
when( wPtr === i.U & ~isFull ){
io.sram(i).wr <> io.sram_w.addrw
io.sram(i).wr <> io.sram_w
}
when( rPtr === i.U & ~isEmpty){

16
src/main/scala/backBoard/shin/SRAMFifo.scala
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@@ -3,23 +3,7 @@ package BACK
import chisel3._
import chisel3.util._
class SRAM2kWRIO extends Bundle {
val addrw = Input(UInt(11.W))
val dataw = Input( UInt(8.W) )
val enw = Input(Bool())
}
class SRAM2kRDIO extends Bundle {
val addrr = Input(UInt(11.W))
val datar = Output( UInt(8.W) )
val enr = Input(Bool())
}
class SRAM2kIO extends Bundle {
val rd = new SRAM2kRDIO
val wr = new SRAM2kWRIO
}
// class SRAM2kFifoIO extends Bundle {
// val sram = new SRAM2kIO

71
src/main/scala/backBoard/shin/ShinTop.scala
View File

@@ -25,15 +25,21 @@ class ShinTopIO extends Bundle{
val timeStamp = Input(UInt(64.W))
val dSMdeq = Input( Vec(4, Bool()) )
val uSMenq = Input( Vec(4, Bool()) )
val sram_w = Vec( 4, new SRAM2kWRIO) //QSPI
val sram_r = Vec( 4, new SRAM2kRDIO) //QSPI
val sram = MixedVec(
Vec(4, new SRAM2kIO)
Vec(4, new SRAM2kIO)
Vec(4, new SRAM2kIO)
Vec(4, new SRAM2kIO)
Vec(2, new SRAM2kIO)
Vec(2, new SRAM2kIO)
Vec(2, new SRAM2kIO)
Vec(2, new SRAM2kIO)
Flipped(Vec(4, new SRAM2kIO)),
Flipped(Vec(4, new SRAM2kIO)),
Flipped(Vec(4, new SRAM2kIO)),
Flipped(Vec(4, new SRAM2kIO)),
Flipped(Vec(2, new SRAM2kIO)),
Flipped(Vec(2, new SRAM2kIO)),
Flipped(Vec(2, new SRAM2kIO)),
Flipped(Vec(2, new SRAM2kIO)),
)
}
@@ -46,18 +52,18 @@ class ShinTop extends Module{
// val CDROut = for( i <- 0 until 2 ) yield { Module(new CDROut) }
val slaveParser = Module(new SlaveParser )
val masterParser = Module(new MasterParser)
// val masterParser = Module(new MasterParser)
val smUnit = Seq(
Module( new SMUnit(depth = 4) )
Module( new SMUnit(depth = 4) )
Module( new SMUnit(depth = 4) )
Module( new SMUnit(depth = 4) )
Module( new SMUnit(depth = 2) )
Module( new SMUnit(depth = 2) )
Module( new SMUnit(depth = 2) )
Module( new SMUnit(depth = 2) )
Module( new SMUnit(depth = 4) ),
Module( new SMUnit(depth = 4) ),
Module( new SMUnit(depth = 4) ),
Module( new SMUnit(depth = 4) ),
Module( new SMUnit(depth = 2) ),
Module( new SMUnit(depth = 2) ),
Module( new SMUnit(depth = 2) ),
Module( new SMUnit(depth = 2) ),
)
@@ -66,16 +72,38 @@ class ShinTop extends Module{
smUnit(4).io.sram_w := slaveParser.io.sram_w(2)
smUnit(6).io.sram_w := slaveParser.io.sram_w(3)
smUnit(0).io.sram_r <> io.sram_r(0)
smUnit(2).io.sram_r <> io.sram_r(1)
smUnit(4).io.sram_r <> io.sram_r(2)
smUnit(6).io.sram_r <> io.sram_r(3)
smUnit(1).io.sram_r <> slaveParser.io.sram_r(0)
smUnit(3).io.sram_r <> slaveParser.io.sram_r(1)
smUnit(5).io.sram_r <> slaveParser.io.sram_r(2)
smUnit(7).io.sram_r <> slaveParser.io.sram_r(3)
smUnit(1).io.sram_w := io.sram_w(0)
smUnit(3).io.sram_w := io.sram_w(1)
smUnit(5).io.sram_w := io.sram_w(2)
smUnit(7).io.sram_w := io.sram_w(3)
smUnit(0).io.enq := slaveParser.io.dSMenq(0)
smUnit(2).io.enq := slaveParser.io.dSMenq(1)
smUnit(4).io.enq := slaveParser.io.dSMenq(2)
smUnit(6).io.enq := slaveParser.io.dSMenq(3)
smUnit(0).io.deq := io.dSMdeq(0)
smUnit(2).io.deq := io.dSMdeq(1)
smUnit(4).io.deq := io.dSMdeq(2)
smUnit(6).io.deq := io.dSMdeq(3)
smUnit(1).io.enq := io.uSMenq(0)
smUnit(3).io.enq := io.uSMenq(1)
smUnit(5).io.enq := io.uSMenq(2)
smUnit(7).io.enq := io.uSMenq(3)
smUnit(1).io.deq := slaveParser.io.uSMdeq(0)
smUnit(3).io.deq := slaveParser.io.uSMdeq(1)
smUnit(5).io.deq := slaveParser.io.uSMdeq(2)
@@ -99,7 +127,14 @@ class ShinTop extends Module{
slaveParser.io.timeStamp := io.timeStamp
slaveParser.io.trigAddr(0) := "hffff".U
slaveParser.io.trigAddr(1) := "hffff".U
slaveParser.io.trigAddr(2) := "hffff".U
slaveParser.io.trigAddr(3) := "hffff".U
slaveParser.io.trigAddr(4) := "hffff".U
slaveParser.io.trigAddr(5) := "hffff".U
slaveParser.io.trigAddr(6) := "hffff".U
slaveParser.io.trigAddr(7) := "hffff".U

31
src/main/scala/backBoard/shin/SlaveParser.scala
View File

@@ -76,6 +76,9 @@ abstract class SlaveParserBase extends Module{
val downSendGen = Module(new SlaveSendGen)
val upSendGen = Module(new SlaveSendGen)
val isReadyToProbe = RegInit(false.B)
val isLastDevice: Bool = RegInit(false.B)
val isDeviceModified: Bool = RegInit(true.B)
val localDevIndex = RegInit(0.U(14.W)) //当前设备索引
dontTouch(localDevIndex)
@@ -141,7 +144,7 @@ abstract class SlaveParserBase extends Module{
isUpSendPend & upRecParser.io.subMsgReq.fire | //上行转发
isReadyToProbe // 上行探针
assert( ~(isUpSendPend & isUpSendProbe), "Assert Failed, Check Softwave, Probe is Sent while transfering!\n" )
assert( ~(isUpSendPend & isReadyToProbe), "Assert Failed, Check Softwave, Probe is Sent while transfering!\n" )
upSendGen.io.frameReq.bits := Mux1H(Seq(
isUpSendPend -> upFrameInfo, //上行转发
@@ -428,14 +431,7 @@ trait SlaveParserRW{ this: SlaveParserBase =>
io.dSMenq(0) := isWrite & isWRSM0 & io.trigAddr(0) === addrw(10,0)
io.uSMdeq(1) := isRead & isRDSM1 & io.trigAddr(1) === readSMAddr(10,0)
io.dSMenq(2) := isWrite & isWRSM2 & io.trigAddr(2) === addrw(10,0)
io.uSMdeq(3) := isRead & isRDSM3 & io.trigAddr(3) === readSMAddr(10,0)
io.dSMenq(4) := isWrite & isWRSM4 & io.trigAddr(4) === addrw(10,0)
io.uSMdeq(5) := isRead & isRDSM5 & io.trigAddr(5) === readSMAddr(10,0)
io.dSMenq(6) := isWrite & isWRSM6 & io.trigAddr(6) === addrw(10,0)
io.uSMdeq(7) := isRead & isRDSM7 & io.trigAddr(7) === readSMAddr(10,0)
@@ -519,6 +515,18 @@ trait SlaveParserRW{ this: SlaveParserBase =>
io.sram_r(1).addrr := readSMAddr(10,0)
io.sram_r(2).addrr := readSMAddr(10,0)
io.sram_r(3).addrr := readSMAddr(10,0)
io.dSMenq(0) := isWrite & isWRSM0 & io.trigAddr(0) === addrw(10,0)
io.uSMdeq(0) := isRead & isRDSM1 & io.trigAddr(1) === readSMAddr(10,0)
io.dSMenq(1) := isWrite & isWRSM2 & io.trigAddr(2) === addrw(10,0)
io.uSMdeq(1) := isRead & isRDSM3 & io.trigAddr(3) === readSMAddr(10,0)
io.dSMenq(2) := isWrite & isWRSM4 & io.trigAddr(4) === addrw(10,0)
io.uSMdeq(2) := isRead & isRDSM5 & io.trigAddr(5) === readSMAddr(10,0)
io.dSMenq(3) := isWrite & isWRSM6 & io.trigAddr(6) === addrw(10,0)
io.uSMdeq(3) := isRead & isRDSM7 & io.trigAddr(7) === readSMAddr(10,0)
}
@@ -618,7 +626,7 @@ trait SlaveParserProbe{ this: SlaveParserBase =>
val isReadyToProbe = RegInit(false.B)
when( downRecParser.io.frameReq.fire & downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //下行来了一个嗅探包
isReadyToProbe := true.B
@@ -634,8 +642,7 @@ trait SlaveParserProbe{ this: SlaveParserBase =>
val isLastDevice: Bool = RegInit(false.B)
val isDeviceModified: Bool = RegInit(true.B)
when( upRecParser.io.frameReq.fire & upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //上行来了一个嗅探包
probeRecCnt := 0.U

3
src/main/scala/backBoard/shin/SlaveRecParser.scala
View File

@@ -86,7 +86,8 @@ class SlaveRecParser extends Module{
io.frameReq.valid := (stateCurr === STATE_HEADER) & (stateNext === STATE_PAYLOAD_INDEX_STYLE)
val frameHeader = Reg(new FrameHeader)
io.frameReq.bits.frameLenAim := frameHeader.frameLenAim
io.frameReq.bits.frameStyle := io.rec.bits.tdata(1,0)
io.frameReq.bits.frameStyle := frameHeader.frameStyle
io.frameReq.bits.frameInfo := frameHeader.frameInfo | io.rec.bits.tdata
io.subMsgReq.valid := (stateCurr === STATE_PAYLOAD_WORKCNT) & (stateNext === STATE_PAYLOAD_DATA)
val subMsgHeader = Reg(new SubMsgHeader)

2
src/test/scala/gcd/test.scala
View File

@@ -102,7 +102,7 @@ object testShinModule extends App {
// ))
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/shin/", "-e", "verilog" ) ++ args, Seq(
ChiselGeneratorAnnotation(() => { new ShinTopIO }),
ChiselGeneratorAnnotation(() => { new ShinTop }),
))