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b55deb239f96178f1b5ffbb3a04d355f7dd8c067
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51 Commits

Author SHA1 Message Date
Ruige Lee
b55deb239f 尝试速率配平，回环改到phy上 2025-05-07 18:12:01 +08:00
Ruige Lee
19f4140dec 尝试加入cdr模块，主站上行rsp， tlast还有亚稳态 2025-05-06 17:39:52 +08:00
Ruige Lee
dabfc86983 发送单元 接收单元代码收尾 2025-04-09 17:29:57 +08:00
Ruige Lee
6c6cce1222 CDRIn采样率改为8x，允许参数化 2025-04-02 15:44:32 +08:00
Ruige Lee
bcb1c8e8f3 修改指令编号 2025-03-04 14:45:31 +08:00
Ruige Lee
46cbd6edec rxFifo bypass to txFifo 2025-03-04 12:01:47 +08:00
Ruige Lee
1c7eb4ce47 使用未使用4b/5b编码作为preamble 2025-03-04 10:58:59 +08:00
Ruige Lee
9937485831 bug修复：定义CDR清中断和中断到来同时发生的行为 2025-02-27 17:27:15 +08:00
Ruige Lee
ea6ea66040 文件结构调整 2025-02-26 15:36:57 +08:00
Ruige Lee
598982cc95 加入中断寄存器，加入两个32bits寄存器 2025-02-20 19:04:30 +08:00
Ruige Lee (WSL)
522d7c19c6 try RoCC 
hack 入，但io如何扇出到顶层？

Revert "hack 入，但io如何扇出到顶层？"

This reverts commit 04dd4dff462b8986d18d13ee7c6b3f17caad247c.

Revert "Revert "hack 入，但io如何扇出到顶层？""

This reverts commit a2fadc0e5524cd292ed245f1fbb5f4a688d95a1d.

CDRIN成功扇出

Rocc仿真环境

扇出RoCC请求返回的FIFO

Revert "扇出RoCC请求返回的FIFO"

This reverts commit c52777091403d300f19935df7b6de3d62c57430b.

RoCC请求返回FIFO使用FLOW模式
 2025-02-20 15:29:04 +08:00
Ruige Lee
6eaaebafcc fifo空间剩余 2025-02-12 16:50:07 +08:00
Ruige Lee
d7effd7543 修正tl2cdr status寄存器访问错误 2025-02-11 17:32:08 +08:00
Ruige Lee
ecff635e83 删除CDR中的硬件CDR 2025-02-11 15:17:02 +08:00
Ruige Lee
94acbfae03 对FSMC的外部IO仿真接线 2025-02-10 11:17:39 +08:00
bacon
fd74e07123 暂时屏蔽了fsmc两个诊断宏，便于调试；增加汇编代码，已经看到Tx0作为下行输出的波形了 2025-02-09 20:08:14 +08:00
Ruige Lee
55675b93c9 txfinish转换为txfinish，同频模式有效 
加入发送接收中断
cdr模块例化代码规范化
 2025-02-08 16:28:42 +08:00
Ruige Lee
1b4243b14d FSMC模块 2025-02-08 15:46:49 +08:00
Ruige Lee
a00223ef8f 4个CDR上下行分离 2025-02-05 18:06:52 +08:00
Ruige Lee
313b7cc11b 增加CDR的约束定时器 2025-01-27 22:26:26 +08:00
Ruige Lee
b75e724948 加入外置CRC32_32 2025-01-24 16:01:10 +08:00
Ruige Lee (WSL)
33f2160365 修复错误位宽，加入islast 2025-01-17 16:21:46 +08:00
Ruige Lee (WSL)
bf0e345cc9 tl2cdr增加附带io 2025-01-16 17:57:44 +08:00
Ruige Lee
981b492a8b 接入TL2CDR 2025-01-10 15:25:10 +08:00
Ruige Lee (WSL)
134440812b compile without tl2cdr 2025-01-09 19:10:07 +08:00
RuigeLee
1ea6ef2596 TL2CDR 2025-01-09 17:39:06 +08:00
RuigeLee
404c973671 使用4b/5b加跳变时钟选择法升级CDR 2025-01-09 17:21:10 +08:00
RuigeLee
394854cdce 回去调spi模块，临时提交，后续需要审查 2024-12-02 15:00:03 +08:00
RuigeLee
2750a8e2f7 规范跨时钟保护，有效果 2024-11-12 17:52:36 +08:00
RuigeLee
392ebf902c 优先级mux引入了额外的一拍数据 2024-11-12 15:55:20 +08:00
RuigeLee
5d6151b2ac 清理代码 2024-11-05 11:13:36 +08:00
RuigeLee
9fa54072f4 bug payload 12bits 
总线握手条件
 2024-11-04 14:39:26 +08:00
RuigeLee
983f9e771d debug开始，cdrin优化后payloadlen加载错误 2024-11-01 18:09:16 +08:00
RuigeLee
46882b6b4d 缩减后面积已经满足要求，时序违例，主要集中在alu和访存接口 2024-10-31 17:38:12 +08:00
RuigeLee
7e99cf4489 1SRAM加入仿真随机初始化；2CDR物理层重新对齐包头 3复制粘贴变量错误 2024-10-17 15:32:16 +08:00
RuigeLee
d449980b5b 物理层和链路层的包头一起合并处理 2024-10-17 11:54:02 +08:00
RuigeLee
a6068fbda0 新主站发送逻辑 2024-10-09 17:37:15 +08:00
RuigeLee
753586a65e 正确锁住，丢包率大 2024-09-23 17:52:59 +08:00
RuigeLee
10b2e4c78f Revert "最后几个比特锁不住" 
This reverts commit 97211f0962.
 2024-09-23 17:40:35 +08:00
RuigeLee
97211f0962 最后几个比特锁不住 2024-09-23 17:40:23 +08:00
RuigeLee
833ad07525 采样头对齐问题，对齐哪个55和D5 2024-09-23 17:23:34 +08:00
RuigeLee
6750593b48 发送改用标志头锁时钟通道方案 2024-09-23 16:44:44 +08:00
RuigeLee
3c357b54e0 4倍频采3次 2024-09-20 14:55:43 +08:00
RuigeLee
1368e9037d CDR基本测试通过 2024-09-19 15:23:38 +08:00
RuigeLee
57c81d5cac CDRin编译通过 2024-09-12 17:48:50 +08:00
RuigeLee
ba6099608c CDR发送测试完成 2024-09-11 17:21:14 +08:00
RuigeLee
7350f3bcf4 仿真，状态机错误 2024-09-10 18:39:35 +08:00
RuigeLee
0080705f0d Revert "重开ebus项目" 
This reverts commit a3234d7f48.
 2024-09-10 16:36:30 +08:00
RuigeLee
a3234d7f48 重开ebus项目 2024-09-10 16:12:18 +08:00
RuigeLee
7aa7ea7ec6 dout增加公共端IO 2024-06-14 19:00:41 +08:00