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仿真，状态机错误

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This commit is contained in:
RuigeLee
2024-09-10 18:39:35 +08:00
parent 0080705f0d
commit 7350f3bcf4
6 changed files with 835 additions and 1 deletions
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14
Makefile
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@@ -1,5 +1,5 @@
.PHONY: compile
.PHONY: compile tb wave
compile:
rm -rf ./generated/
@@ -116,4 +116,16 @@ VSimBack:
tb:
cp ./generated/cdr/CDROut.v ./tb
iverilog -Wall \
-o ./build/wave.iverilog \
-y ./tb \
-I ./tb \
-D RANDOMIZE_REG_INIT \
./tb/cdrOut_tb.v
vvp -N ./build/wave.iverilog -lxt2
vcd:
gtkwave ./build/wave.vcd &

105
src/main/scala/backBoard/ebus/CDROut.scala Normal file
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@@ -0,0 +1,105 @@
package BACK
import chisel3._
import chisel3.util._
class AXIS_Bundle extends Bundle{
val tdata = UInt(8.W)
val tlast = Bool()
val tuser = Bool()
}
//work in 100MHZ
class CDROutIO extends Bundle{
val axis = Flipped(Decoupled(new AXIS_Bundle))
val serDat = Output(Bool())
}
class CDROut extends Module{
val io: CDROutIO = IO(new CDROutIO)
val crcUnit = Module(new crc32_8)
def STATE_IDLE = 0.U
def STATE_PREAMBLE = 1.U
def STATE_PAYLOAD = 2.U
def STATE_FCS = 3.U
val ETH_PRE = "h55".U
val ETH_SFD = "hD5".U
val stateNext = Wire(UInt(2.W))
val stateCurr = RegNext( stateNext, 0.U )
val bitCnt = Reg(UInt(3.W))
val byteCnt = Reg(UInt(16.W))
val crcOut = crcUnit.io.crc
val reset_crc = stateCurr === STATE_IDLE
crcUnit.reset := reset.asBool | reset_crc
crcUnit.io.dataIn := io.axis.bits.tdata
crcUnit.io.isEnable := io.axis.fire
val shiftData = RegInit(0.U(8.W))
stateNext := Mux1H(Seq(
(stateCurr === STATE_IDLE) -> ( Mux( io.axis.valid, STATE_PREAMBLE, STATE_IDLE )),
(stateCurr === STATE_PREAMBLE) -> ( Mux( byteCnt === 7.U & bitCnt === 7.U, STATE_PAYLOAD, STATE_PREAMBLE )),
(stateCurr === STATE_PAYLOAD) -> ( Mux( io.axis.fire, Mux( io.axis.bits.tlast, STATE_FCS, STATE_PAYLOAD ), STATE_FCS ) ),
(stateCurr === STATE_FCS) -> ( Mux( byteCnt === 3.U & bitCnt === 7.U, STATE_FCS, STATE_IDLE )),
))
io.serDat := shiftData.extract(7)
io.axis.ready :=
bitCnt === 7.U & (
(stateCurr === STATE_PREAMBLE & byteCnt === 7.U) |
(stateCurr === STATE_PAYLOAD)
)
when( stateCurr === STATE_IDLE & stateNext === STATE_PREAMBLE){ //PRE
shiftData := ETH_PRE
} .otherwise{
when( bitCnt =/= 7.U ){
shiftData := shiftData << 1
} .otherwise{ //bitCnt === 7.U
when( stateCurr === STATE_PREAMBLE ){
shiftData := MuxCase( ETH_PRE, Array(
( byteCnt === 6.U ) -> ETH_SFD,
( byteCnt === 7.U ) -> io.axis.bits.tdata,
))
} .elsewhen( stateCurr === STATE_PAYLOAD ){
shiftData := io.axis.bits.tdata
} .elsewhen( stateCurr === STATE_FCS ){
shiftData := Mux1H(Seq(
( byteCnt === 0.U) -> ~crcOut( 7,0),
( byteCnt === 1.U) -> ~crcOut(15,8),
( byteCnt === 2.U) -> ~crcOut(23,16),
( byteCnt === 3.U) -> ~crcOut(31,24),
))
}
}
}
when( stateCurr === STATE_IDLE ){ //PRE
bitCnt := 0.U
} .otherwise{
bitCnt := bitCnt + 1.U
}
when( stateNext =/= stateCurr ){
byteCnt := 0.U
} .elsewhen( bitCnt === 7.U ){
byteCnt := byteCnt + 1.U
}
}

141
src/main/scala/backBoard/ebus/crc32.scala Normal file
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@@ -0,0 +1,141 @@
package BACK
import chisel3._
import chisel3.util._
// module eth_crc (Clk, Reset, Data, Enable, Initialize, Crc, CrcError);
// input Clk;
// input Reset;
// input [3:0] Data;
// input Enable;
// input Initialize;
// output [31:0] Crc;
// output CrcError;
// reg [31:0] Crc;
// wire [31:0] CrcNext;
// assign CrcNext[0] = Enable & (Data[0] ^ Crc[28]);
// assign CrcNext[1] = Enable & (Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29]);
// assign CrcNext[2] = Enable & (Data[2] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[30]);
// assign CrcNext[3] = Enable & (Data[3] ^ Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30] ^ Crc[31]);
// assign CrcNext[4] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[0];
// assign CrcNext[5] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[1];
// assign CrcNext[6] = (Enable & (Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30])) ^ Crc[ 2];
// assign CrcNext[7] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[3];
// assign CrcNext[8] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[4];
// assign CrcNext[9] = (Enable & (Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30])) ^ Crc[5];
// assign CrcNext[10] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[6];
// assign CrcNext[11] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[7];
// assign CrcNext[12] = (Enable & (Data[2] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[30])) ^ Crc[8];
// assign CrcNext[13] = (Enable & (Data[3] ^ Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30] ^ Crc[31])) ^ Crc[9];
// assign CrcNext[14] = (Enable & (Data[3] ^ Data[2] ^ Crc[30] ^ Crc[31])) ^ Crc[10];
// assign CrcNext[15] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[11];
// assign CrcNext[16] = (Enable & (Data[0] ^ Crc[28])) ^ Crc[12];
// assign CrcNext[17] = (Enable & (Data[1] ^ Crc[29])) ^ Crc[13];
// assign CrcNext[18] = (Enable & (Data[2] ^ Crc[30])) ^ Crc[14];
// assign CrcNext[19] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[15];
// assign CrcNext[20] = Crc[16];
// assign CrcNext[21] = Crc[17];
// assign CrcNext[22] = (Enable & (Data[0] ^ Crc[28])) ^ Crc[18];
// assign CrcNext[23] = (Enable & (Data[1] ^ Data[0] ^ Crc[29] ^ Crc[28])) ^ Crc[19];
// assign CrcNext[24] = (Enable & (Data[2] ^ Data[1] ^ Crc[30] ^ Crc[29])) ^ Crc[20];
// assign CrcNext[25] = (Enable & (Data[3] ^ Data[2] ^ Crc[31] ^ Crc[30])) ^ Crc[21];
// assign CrcNext[26] = (Enable & (Data[3] ^ Data[0] ^ Crc[31] ^ Crc[28])) ^ Crc[22];
// assign CrcNext[27] = (Enable & (Data[1] ^ Crc[29])) ^ Crc[23];
// assign CrcNext[28] = (Enable & (Data[2] ^ Crc[30])) ^ Crc[24];
// assign CrcNext[29] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[25];
// assign CrcNext[30] = Crc[26];
// assign CrcNext[31] = Crc[27];
// always @ (posedge Clk or posedge Reset)
// begin
// if (Reset)
// Crc <= 32'hffffffff;
// else
// if(Initialize)
// Crc <= 32'hffffffff;
// else
// Crc <= CrcNext;
// end
// assign CrcError = Crc[31:0] != 32'hc704dd7b; // CRC not equal to magic number
// endmodule
//-----------------------------------------------------------------------------
// Copyright (C) 2009 OutputLogic.com
// This source file may be used and distributed without restriction
// provided that this copyright statement is not removed from the file
// and that any derivative work contains the original copyright notice
// and the associated disclaimer.
//
// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
//-----------------------------------------------------------------------------
// CRC module for data[7:0] , crc[31:0]=1+x^1+x^2+x^4+x^5+x^7+x^8+x^10+x^11+x^12+x^16+x^22+x^23+x^26+x^32;
//-----------------------------------------------------------------------------
class crc32_8() extends Module{
class crc32IO_Bundle extends Bundle{
val isEnable = Input(Bool())
val dataIn = Input(UInt(8.W))
val crc = Output(UInt(32.W))
}
val io = IO( new crc32IO_Bundle )
// val LFSR_POLY = "h4c11db7".U
val lfsr_c = for( i <- 0 until 32 ) yield Wire(Bool())
val lfsr_q = for( i <- 0 until 32 ) yield RegEnable( lfsr_c(i), true.B, io.isEnable )
io.crc := Cat( lfsr_q.reverse )
lfsr_c( 0) := lfsr_q(24) ^ lfsr_q(30) ^ io.dataIn(0) ^ io.dataIn(6)
lfsr_c( 1) := lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(30) ^ lfsr_q(31) ^ io.dataIn(0) ^ io.dataIn(1) ^ io.dataIn(6) ^ io.dataIn(7)
lfsr_c( 2) := lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(30) ^ lfsr_q(31) ^ io.dataIn(0) ^ io.dataIn(1) ^ io.dataIn(2) ^ io.dataIn(6) ^ io.dataIn(7)
lfsr_c( 3) := lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(27) ^ lfsr_q(31) ^ io.dataIn(1) ^ io.dataIn(2) ^ io.dataIn(3) ^ io.dataIn(7)
lfsr_c( 4) := lfsr_q(24) ^ lfsr_q(26) ^ lfsr_q(27) ^ lfsr_q(28) ^ lfsr_q(30) ^ io.dataIn(0) ^ io.dataIn(2) ^ io.dataIn(3) ^ io.dataIn(4) ^ io.dataIn(6)
lfsr_c( 5) := lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(27) ^ lfsr_q(28) ^ lfsr_q(29) ^ lfsr_q(30) ^ lfsr_q(31) ^ io.dataIn(0) ^ io.dataIn(1) ^ io.dataIn(3) ^ io.dataIn(4) ^ io.dataIn(5) ^ io.dataIn(6) ^ io.dataIn(7)
lfsr_c( 6) := lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(28) ^ lfsr_q(29) ^ lfsr_q(30) ^ lfsr_q(31) ^ io.dataIn(1) ^ io.dataIn(2) ^ io.dataIn(4) ^ io.dataIn(5) ^ io.dataIn(6) ^ io.dataIn(7)
lfsr_c( 7) := lfsr_q(24) ^ lfsr_q(26) ^ lfsr_q(27) ^ lfsr_q(29) ^ lfsr_q(31) ^ io.dataIn(0) ^ io.dataIn(2) ^ io.dataIn(3) ^ io.dataIn(5) ^ io.dataIn(7)
lfsr_c( 8) := lfsr_q( 0) ^ lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(27) ^ lfsr_q(28) ^ io.dataIn(0) ^ io.dataIn(1) ^ io.dataIn(3) ^ io.dataIn(4)
lfsr_c( 9) := lfsr_q( 1) ^ lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(28) ^ lfsr_q(29) ^ io.dataIn(1) ^ io.dataIn(2) ^ io.dataIn(4) ^ io.dataIn(5)
lfsr_c(10) := lfsr_q( 2) ^ lfsr_q(24) ^ lfsr_q(26) ^ lfsr_q(27) ^ lfsr_q(29) ^ io.dataIn(0) ^ io.dataIn(2) ^ io.dataIn(3) ^ io.dataIn(5)
lfsr_c(11) := lfsr_q( 3) ^ lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(27) ^ lfsr_q(28) ^ io.dataIn(0) ^ io.dataIn(1) ^ io.dataIn(3) ^ io.dataIn(4)
lfsr_c(12) := lfsr_q( 4) ^ lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(28) ^ lfsr_q(29) ^ lfsr_q(30) ^ io.dataIn(0) ^ io.dataIn(1) ^ io.dataIn(2) ^ io.dataIn(4) ^ io.dataIn(5) ^ io.dataIn(6)
lfsr_c(13) := lfsr_q( 5) ^ lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(27) ^ lfsr_q(29) ^ lfsr_q(30) ^ lfsr_q(31) ^ io.dataIn(1) ^ io.dataIn(2) ^ io.dataIn(3) ^ io.dataIn(5) ^ io.dataIn(6) ^ io.dataIn(7)
lfsr_c(14) := lfsr_q( 6) ^ lfsr_q(26) ^ lfsr_q(27) ^ lfsr_q(28) ^ lfsr_q(30) ^ lfsr_q(31) ^ io.dataIn(2) ^ io.dataIn(3) ^ io.dataIn(4) ^ io.dataIn(6) ^ io.dataIn(7)
lfsr_c(15) := lfsr_q( 7) ^ lfsr_q(27) ^ lfsr_q(28) ^ lfsr_q(29) ^ lfsr_q(31) ^ io.dataIn(3) ^ io.dataIn(4) ^ io.dataIn(5) ^ io.dataIn(7)
lfsr_c(16) := lfsr_q( 8) ^ lfsr_q(24) ^ lfsr_q(28) ^ lfsr_q(29) ^ io.dataIn(0) ^ io.dataIn(4) ^ io.dataIn(5)
lfsr_c(17) := lfsr_q( 9) ^ lfsr_q(25) ^ lfsr_q(29) ^ lfsr_q(30) ^ io.dataIn(1) ^ io.dataIn(5) ^ io.dataIn(6)
lfsr_c(18) := lfsr_q(10) ^ lfsr_q(26) ^ lfsr_q(30) ^ lfsr_q(31) ^ io.dataIn(2) ^ io.dataIn(6) ^ io.dataIn(7)
lfsr_c(19) := lfsr_q(11) ^ lfsr_q(27) ^ lfsr_q(31) ^ io.dataIn(3) ^ io.dataIn(7)
lfsr_c(20) := lfsr_q(12) ^ lfsr_q(28) ^ io.dataIn(4)
lfsr_c(21) := lfsr_q(13) ^ lfsr_q(29) ^ io.dataIn(5)
lfsr_c(22) := lfsr_q(14) ^ lfsr_q(24) ^ io.dataIn(0)
lfsr_c(23) := lfsr_q(15) ^ lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(30) ^ io.dataIn(0) ^ io.dataIn(1) ^ io.dataIn(6)
lfsr_c(24) := lfsr_q(16) ^ lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(31) ^ io.dataIn(1) ^ io.dataIn(2) ^ io.dataIn(7)
lfsr_c(25) := lfsr_q(17) ^ lfsr_q(26) ^ lfsr_q(27) ^ io.dataIn(2) ^ io.dataIn(3)
lfsr_c(26) := lfsr_q(18) ^ lfsr_q(24) ^ lfsr_q(27) ^ lfsr_q(28) ^ lfsr_q(30) ^ io.dataIn(0) ^ io.dataIn(3) ^ io.dataIn(4) ^ io.dataIn(6)
lfsr_c(27) := lfsr_q(19) ^ lfsr_q(25) ^ lfsr_q(28) ^ lfsr_q(29) ^ lfsr_q(31) ^ io.dataIn(1) ^ io.dataIn(4) ^ io.dataIn(5) ^ io.dataIn(7)
lfsr_c(28) := lfsr_q(20) ^ lfsr_q(26) ^ lfsr_q(29) ^ lfsr_q(30) ^ io.dataIn(2) ^ io.dataIn(5) ^ io.dataIn(6)
lfsr_c(29) := lfsr_q(21) ^ lfsr_q(27) ^ lfsr_q(30) ^ lfsr_q(31) ^ io.dataIn(3) ^ io.dataIn(6) ^ io.dataIn(7)
lfsr_c(30) := lfsr_q(22) ^ lfsr_q(28) ^ lfsr_q(31) ^ io.dataIn(4) ^ io.dataIn(7)
lfsr_c(31) := lfsr_q(23) ^ lfsr_q(29) ^ io.dataIn(5)
}

3
src/test/scala/gcd/test.scala
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@@ -38,6 +38,9 @@ object testModule extends App {
))
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-E", "verilog" ) ++ args, Seq(
ChiselGeneratorAnnotation(() => { new CDROut })
))
// (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
// ChiselGeneratorAnnotation(() => { new BackPlaneChainTest })

460
tb/CDROut.v Normal file
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@@ -0,0 +1,460 @@
module crc32_8(
input clock,
input reset,
input io_isEnable,
input [7:0] io_dataIn,
output [31:0] io_crc
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
reg [31:0] _RAND_3;
reg [31:0] _RAND_4;
reg [31:0] _RAND_5;
reg [31:0] _RAND_6;
reg [31:0] _RAND_7;
reg [31:0] _RAND_8;
reg [31:0] _RAND_9;
reg [31:0] _RAND_10;
reg [31:0] _RAND_11;
reg [31:0] _RAND_12;
reg [31:0] _RAND_13;
reg [31:0] _RAND_14;
reg [31:0] _RAND_15;
reg [31:0] _RAND_16;
reg [31:0] _RAND_17;
reg [31:0] _RAND_18;
reg [31:0] _RAND_19;
reg [31:0] _RAND_20;
reg [31:0] _RAND_21;
reg [31:0] _RAND_22;
reg [31:0] _RAND_23;
reg [31:0] _RAND_24;
reg [31:0] _RAND_25;
reg [31:0] _RAND_26;
reg [31:0] _RAND_27;
reg [31:0] _RAND_28;
reg [31:0] _RAND_29;
reg [31:0] _RAND_30;
reg [31:0] _RAND_31;
`endif // RANDOMIZE_REG_INIT
reg lfsr_q_0; // @[Reg.scala 35:20]
reg lfsr_q_24; // @[Reg.scala 35:20]
reg lfsr_q_30; // @[Reg.scala 35:20]
wire lfsr_c_0 = lfsr_q_24 ^ lfsr_q_30 ^ io_dataIn[0] ^ io_dataIn[6]; // @[crc32.scala 106:56]
wire _GEN_0 = io_isEnable ? lfsr_c_0 : lfsr_q_0; // @[Reg.scala 36:18 35:20 36:22]
reg lfsr_q_1; // @[Reg.scala 35:20]
reg lfsr_q_25; // @[Reg.scala 35:20]
wire _lfsr_c_1_T = lfsr_q_24 ^ lfsr_q_25; // @[crc32.scala 107:28]
reg lfsr_q_31; // @[Reg.scala 35:20]
wire lfsr_c_1 = lfsr_q_24 ^ lfsr_q_25 ^ lfsr_q_30 ^ lfsr_q_31 ^ io_dataIn[0] ^ io_dataIn[1] ^ io_dataIn[6] ^
io_dataIn[7]; // @[crc32.scala 107:112]
wire _GEN_1 = io_isEnable ? lfsr_c_1 : lfsr_q_1; // @[Reg.scala 36:18 35:20 36:22]
reg lfsr_q_2; // @[Reg.scala 35:20]
reg lfsr_q_26; // @[Reg.scala 35:20]
wire lfsr_c_2 = _lfsr_c_1_T ^ lfsr_q_26 ^ lfsr_q_30 ^ lfsr_q_31 ^ io_dataIn[0] ^ io_dataIn[1] ^ io_dataIn[2] ^
io_dataIn[6] ^ io_dataIn[7]; // @[crc32.scala 108:140]
wire _GEN_2 = io_isEnable ? lfsr_c_2 : lfsr_q_2; // @[Reg.scala 36:18 35:20 36:22]
reg lfsr_q_3; // @[Reg.scala 35:20]
wire _lfsr_c_3_T = lfsr_q_25 ^ lfsr_q_26; // @[crc32.scala 109:28]
reg lfsr_q_27; // @[Reg.scala 35:20]
wire lfsr_c_3 = lfsr_q_25 ^ lfsr_q_26 ^ lfsr_q_27 ^ lfsr_q_31 ^ io_dataIn[1] ^ io_dataIn[2] ^ io_dataIn[3] ^
io_dataIn[7]; // @[crc32.scala 109:112]
wire _GEN_3 = io_isEnable ? lfsr_c_3 : lfsr_q_3; // @[Reg.scala 36:18 35:20 36:22]
reg lfsr_q_4; // @[Reg.scala 35:20]
wire _lfsr_c_4_T_1 = lfsr_q_24 ^ lfsr_q_26 ^ lfsr_q_27; // @[crc32.scala 110:41]
reg lfsr_q_28; // @[Reg.scala 35:20]
wire lfsr_c_4 = lfsr_q_24 ^ lfsr_q_26 ^ lfsr_q_27 ^ lfsr_q_28 ^ lfsr_q_30 ^ io_dataIn[0] ^ io_dataIn[2] ^ io_dataIn[3
] ^ io_dataIn[4] ^ io_dataIn[6]; // @[crc32.scala 110:140]
wire _GEN_4 = io_isEnable ? lfsr_c_4 : lfsr_q_4; // @[Reg.scala 36:18 35:20 36:22]
reg lfsr_q_5; // @[Reg.scala 35:20]
reg lfsr_q_29; // @[Reg.scala 35:20]
wire lfsr_c_5 = _lfsr_c_1_T ^ lfsr_q_27 ^ lfsr_q_28 ^ lfsr_q_29 ^ lfsr_q_30 ^ lfsr_q_31 ^ io_dataIn[0] ^ io_dataIn[1]
^ io_dataIn[3] ^ io_dataIn[4] ^ io_dataIn[5] ^ io_dataIn[6] ^ io_dataIn[7]; // @[crc32.scala 111:196]
wire _GEN_5 = io_isEnable ? lfsr_c_5 : lfsr_q_5; // @[Reg.scala 36:18 35:20 36:22]
reg lfsr_q_6; // @[Reg.scala 35:20]
wire lfsr_c_6 = _lfsr_c_3_T ^ lfsr_q_28 ^ lfsr_q_29 ^ lfsr_q_30 ^ lfsr_q_31 ^ io_dataIn[1] ^ io_dataIn[2] ^ io_dataIn
[4] ^ io_dataIn[5] ^ io_dataIn[6] ^ io_dataIn[7]; // @[crc32.scala 112:168]
wire _GEN_6 = io_isEnable ? lfsr_c_6 : lfsr_q_6; // @[Reg.scala 36:18 35:20 36:22]
reg lfsr_q_7; // @[Reg.scala 35:20]
wire lfsr_c_7 = _lfsr_c_4_T_1 ^ lfsr_q_29 ^ lfsr_q_31 ^ io_dataIn[0] ^ io_dataIn[2] ^ io_dataIn[3] ^ io_dataIn[5] ^
io_dataIn[7]; // @[crc32.scala 113:140]
wire _GEN_7 = io_isEnable ? lfsr_c_7 : lfsr_q_7; // @[Reg.scala 36:18 35:20 36:22]
reg lfsr_q_8; // @[Reg.scala 35:20]
wire lfsr_c_8 = lfsr_q_0 ^ lfsr_q_24 ^ lfsr_q_25 ^ lfsr_q_27 ^ lfsr_q_28 ^ io_dataIn[0] ^ io_dataIn[1] ^ io_dataIn[3]
^ io_dataIn[4]; // @[crc32.scala 114:125]
wire _GEN_8 = io_isEnable ? lfsr_c_8 : lfsr_q_8; // @[Reg.scala 36:18 35:20 36:22]
reg lfsr_q_9; // @[Reg.scala 35:20]
wire lfsr_c_9 = lfsr_q_1 ^ lfsr_q_25 ^ lfsr_q_26 ^ lfsr_q_28 ^ lfsr_q_29 ^ io_dataIn[1] ^ io_dataIn[2] ^ io_dataIn[4]
^ io_dataIn[5]; // @[crc32.scala 115:125]
wire _GEN_9 = io_isEnable ? lfsr_c_9 : lfsr_q_9; // @[Reg.scala 36:18 35:20 36:22]
reg lfsr_q_10; // @[Reg.scala 35:20]
wire lfsr_c_10 = lfsr_q_2 ^ lfsr_q_24 ^ lfsr_q_26 ^ lfsr_q_27 ^ lfsr_q_29 ^ io_dataIn[0] ^ io_dataIn[2] ^ io_dataIn[3
] ^ io_dataIn[5]; // @[crc32.scala 116:125]
wire _GEN_10 = io_isEnable ? lfsr_c_10 : lfsr_q_10; // @[Reg.scala 36:18 35:20 36:22]
reg lfsr_q_11; // @[Reg.scala 35:20]
wire lfsr_c_11 = lfsr_q_3 ^ lfsr_q_24 ^ lfsr_q_25 ^ lfsr_q_27 ^ lfsr_q_28 ^ io_dataIn[0] ^ io_dataIn[1] ^ io_dataIn[3
] ^ io_dataIn[4]; // @[crc32.scala 117:125]
wire _GEN_11 = io_isEnable ? lfsr_c_11 : lfsr_q_11; // @[Reg.scala 36:18 35:20 36:22]
reg lfsr_q_12; // @[Reg.scala 35:20]
wire lfsr_c_12 = lfsr_q_4 ^ lfsr_q_24 ^ lfsr_q_25 ^ lfsr_q_26 ^ lfsr_q_28 ^ lfsr_q_29 ^ lfsr_q_30 ^ io_dataIn[0] ^
io_dataIn[1] ^ io_dataIn[2] ^ io_dataIn[4] ^ io_dataIn[5] ^ io_dataIn[6]; // @[crc32.scala 118:181]
wire _GEN_12 = io_isEnable ? lfsr_c_12 : lfsr_q_12; // @[Reg.scala 36:18 35:20 36:22]
reg lfsr_q_13; // @[Reg.scala 35:20]
wire lfsr_c_13 = lfsr_q_5 ^ lfsr_q_25 ^ lfsr_q_26 ^ lfsr_q_27 ^ lfsr_q_29 ^ lfsr_q_30 ^ lfsr_q_31 ^ io_dataIn[1] ^
io_dataIn[2] ^ io_dataIn[3] ^ io_dataIn[5] ^ io_dataIn[6] ^ io_dataIn[7]; // @[crc32.scala 119:181]
wire _GEN_13 = io_isEnable ? lfsr_c_13 : lfsr_q_13; // @[Reg.scala 36:18 35:20 36:22]
reg lfsr_q_14; // @[Reg.scala 35:20]
wire lfsr_c_14 = lfsr_q_6 ^ lfsr_q_26 ^ lfsr_q_27 ^ lfsr_q_28 ^ lfsr_q_30 ^ lfsr_q_31 ^ io_dataIn[2] ^ io_dataIn[3]
^ io_dataIn[4] ^ io_dataIn[6] ^ io_dataIn[7]; // @[crc32.scala 120:153]
wire _GEN_14 = io_isEnable ? lfsr_c_14 : lfsr_q_14; // @[Reg.scala 36:18 35:20 36:22]
reg lfsr_q_15; // @[Reg.scala 35:20]
wire lfsr_c_15 = lfsr_q_7 ^ lfsr_q_27 ^ lfsr_q_28 ^ lfsr_q_29 ^ lfsr_q_31 ^ io_dataIn[3] ^ io_dataIn[4] ^ io_dataIn[5
] ^ io_dataIn[7]; // @[crc32.scala 121:125]
wire _GEN_15 = io_isEnable ? lfsr_c_15 : lfsr_q_15; // @[Reg.scala 36:18 35:20 36:22]
reg lfsr_q_16; // @[Reg.scala 35:20]
wire lfsr_c_16 = lfsr_q_8 ^ lfsr_q_24 ^ lfsr_q_28 ^ lfsr_q_29 ^ io_dataIn[0] ^ io_dataIn[4] ^ io_dataIn[5]; // @[crc32.scala 122:97]
wire _GEN_16 = io_isEnable ? lfsr_c_16 : lfsr_q_16; // @[Reg.scala 36:18 35:20 36:22]
reg lfsr_q_17; // @[Reg.scala 35:20]
wire lfsr_c_17 = lfsr_q_9 ^ lfsr_q_25 ^ lfsr_q_29 ^ lfsr_q_30 ^ io_dataIn[1] ^ io_dataIn[5] ^ io_dataIn[6]; // @[crc32.scala 123:97]
wire _GEN_17 = io_isEnable ? lfsr_c_17 : lfsr_q_17; // @[Reg.scala 36:18 35:20 36:22]
reg lfsr_q_18; // @[Reg.scala 35:20]
wire lfsr_c_18 = lfsr_q_10 ^ lfsr_q_26 ^ lfsr_q_30 ^ lfsr_q_31 ^ io_dataIn[2] ^ io_dataIn[6] ^ io_dataIn[7]; // @[crc32.scala 124:97]
wire _GEN_18 = io_isEnable ? lfsr_c_18 : lfsr_q_18; // @[Reg.scala 36:18 35:20 36:22]
reg lfsr_q_19; // @[Reg.scala 35:20]
wire lfsr_c_19 = lfsr_q_11 ^ lfsr_q_27 ^ lfsr_q_31 ^ io_dataIn[3] ^ io_dataIn[7]; // @[crc32.scala 125:69]
wire _GEN_19 = io_isEnable ? lfsr_c_19 : lfsr_q_19; // @[Reg.scala 36:18 35:20 36:22]
reg lfsr_q_20; // @[Reg.scala 35:20]
wire lfsr_c_20 = lfsr_q_12 ^ lfsr_q_28 ^ io_dataIn[4]; // @[crc32.scala 126:41]
wire _GEN_20 = io_isEnable ? lfsr_c_20 : lfsr_q_20; // @[Reg.scala 36:18 35:20 36:22]
reg lfsr_q_21; // @[Reg.scala 35:20]
wire lfsr_c_21 = lfsr_q_13 ^ lfsr_q_29 ^ io_dataIn[5]; // @[crc32.scala 127:41]
wire _GEN_21 = io_isEnable ? lfsr_c_21 : lfsr_q_21; // @[Reg.scala 36:18 35:20 36:22]
reg lfsr_q_22; // @[Reg.scala 35:20]
wire lfsr_c_22 = lfsr_q_14 ^ lfsr_q_24 ^ io_dataIn[0]; // @[crc32.scala 128:41]
wire _GEN_22 = io_isEnable ? lfsr_c_22 : lfsr_q_22; // @[Reg.scala 36:18 35:20 36:22]
reg lfsr_q_23; // @[Reg.scala 35:20]
wire lfsr_c_23 = lfsr_q_15 ^ lfsr_q_24 ^ lfsr_q_25 ^ lfsr_q_30 ^ io_dataIn[0] ^ io_dataIn[1] ^ io_dataIn[6]; // @[crc32.scala 129:97]
wire _GEN_23 = io_isEnable ? lfsr_c_23 : lfsr_q_23; // @[Reg.scala 36:18 35:20 36:22]
wire lfsr_c_24 = lfsr_q_16 ^ lfsr_q_25 ^ lfsr_q_26 ^ lfsr_q_31 ^ io_dataIn[1] ^ io_dataIn[2] ^ io_dataIn[7]; // @[crc32.scala 130:97]
wire _GEN_24 = io_isEnable ? lfsr_c_24 : lfsr_q_24; // @[Reg.scala 36:18 35:20 36:22]
wire lfsr_c_25 = lfsr_q_17 ^ lfsr_q_26 ^ lfsr_q_27 ^ io_dataIn[2] ^ io_dataIn[3]; // @[crc32.scala 131:69]
wire _GEN_25 = io_isEnable ? lfsr_c_25 : lfsr_q_25; // @[Reg.scala 36:18 35:20 36:22]
wire lfsr_c_26 = lfsr_q_18 ^ lfsr_q_24 ^ lfsr_q_27 ^ lfsr_q_28 ^ lfsr_q_30 ^ io_dataIn[0] ^ io_dataIn[3] ^ io_dataIn[
4] ^ io_dataIn[6]; // @[crc32.scala 132:125]
wire _GEN_26 = io_isEnable ? lfsr_c_26 : lfsr_q_26; // @[Reg.scala 36:18 35:20 36:22]
wire lfsr_c_27 = lfsr_q_19 ^ lfsr_q_25 ^ lfsr_q_28 ^ lfsr_q_29 ^ lfsr_q_31 ^ io_dataIn[1] ^ io_dataIn[4] ^ io_dataIn[
5] ^ io_dataIn[7]; // @[crc32.scala 133:125]
wire _GEN_27 = io_isEnable ? lfsr_c_27 : lfsr_q_27; // @[Reg.scala 36:18 35:20 36:22]
wire lfsr_c_28 = lfsr_q_20 ^ lfsr_q_26 ^ lfsr_q_29 ^ lfsr_q_30 ^ io_dataIn[2] ^ io_dataIn[5] ^ io_dataIn[6]; // @[crc32.scala 134:97]
wire _GEN_28 = io_isEnable ? lfsr_c_28 : lfsr_q_28; // @[Reg.scala 36:18 35:20 36:22]
wire lfsr_c_29 = lfsr_q_21 ^ lfsr_q_27 ^ lfsr_q_30 ^ lfsr_q_31 ^ io_dataIn[3] ^ io_dataIn[6] ^ io_dataIn[7]; // @[crc32.scala 135:97]
wire _GEN_29 = io_isEnable ? lfsr_c_29 : lfsr_q_29; // @[Reg.scala 36:18 35:20 36:22]
wire lfsr_c_30 = lfsr_q_22 ^ lfsr_q_28 ^ lfsr_q_31 ^ io_dataIn[4] ^ io_dataIn[7]; // @[crc32.scala 136:69]
wire _GEN_30 = io_isEnable ? lfsr_c_30 : lfsr_q_30; // @[Reg.scala 36:18 35:20 36:22]
wire lfsr_c_31 = lfsr_q_23 ^ lfsr_q_29 ^ io_dataIn[5]; // @[crc32.scala 137:41]
wire _GEN_31 = io_isEnable ? lfsr_c_31 : lfsr_q_31; // @[Reg.scala 36:18 35:20 36:22]
wire [7:0] io_crc_lo_lo = {lfsr_q_7,lfsr_q_6,lfsr_q_5,lfsr_q_4,lfsr_q_3,lfsr_q_2,lfsr_q_1,lfsr_q_0}; // @[Cat.scala 33:92]
wire [15:0] io_crc_lo = {lfsr_q_15,lfsr_q_14,lfsr_q_13,lfsr_q_12,lfsr_q_11,lfsr_q_10,lfsr_q_9,lfsr_q_8,io_crc_lo_lo}; // @[Cat.scala 33:92]
wire [7:0] io_crc_hi_lo = {lfsr_q_23,lfsr_q_22,lfsr_q_21,lfsr_q_20,lfsr_q_19,lfsr_q_18,lfsr_q_17,lfsr_q_16}; // @[Cat.scala 33:92]
wire [15:0] io_crc_hi = {lfsr_q_31,lfsr_q_30,lfsr_q_29,lfsr_q_28,lfsr_q_27,lfsr_q_26,lfsr_q_25,lfsr_q_24,io_crc_hi_lo}
; // @[Cat.scala 33:92]
assign io_crc = {io_crc_hi,io_crc_lo}; // @[Cat.scala 33:92]
always @(posedge clock) begin
lfsr_q_0 <= reset | _GEN_0; // @[Reg.scala 35:{20,20}]
lfsr_q_24 <= reset | _GEN_24; // @[Reg.scala 35:{20,20}]
lfsr_q_30 <= reset | _GEN_30; // @[Reg.scala 35:{20,20}]
lfsr_q_1 <= reset | _GEN_1; // @[Reg.scala 35:{20,20}]
lfsr_q_25 <= reset | _GEN_25; // @[Reg.scala 35:{20,20}]
lfsr_q_31 <= reset | _GEN_31; // @[Reg.scala 35:{20,20}]
lfsr_q_2 <= reset | _GEN_2; // @[Reg.scala 35:{20,20}]
lfsr_q_26 <= reset | _GEN_26; // @[Reg.scala 35:{20,20}]
lfsr_q_3 <= reset | _GEN_3; // @[Reg.scala 35:{20,20}]
lfsr_q_27 <= reset | _GEN_27; // @[Reg.scala 35:{20,20}]
lfsr_q_4 <= reset | _GEN_4; // @[Reg.scala 35:{20,20}]
lfsr_q_28 <= reset | _GEN_28; // @[Reg.scala 35:{20,20}]
lfsr_q_5 <= reset | _GEN_5; // @[Reg.scala 35:{20,20}]
lfsr_q_29 <= reset | _GEN_29; // @[Reg.scala 35:{20,20}]
lfsr_q_6 <= reset | _GEN_6; // @[Reg.scala 35:{20,20}]
lfsr_q_7 <= reset | _GEN_7; // @[Reg.scala 35:{20,20}]
lfsr_q_8 <= reset | _GEN_8; // @[Reg.scala 35:{20,20}]
lfsr_q_9 <= reset | _GEN_9; // @[Reg.scala 35:{20,20}]
lfsr_q_10 <= reset | _GEN_10; // @[Reg.scala 35:{20,20}]
lfsr_q_11 <= reset | _GEN_11; // @[Reg.scala 35:{20,20}]
lfsr_q_12 <= reset | _GEN_12; // @[Reg.scala 35:{20,20}]
lfsr_q_13 <= reset | _GEN_13; // @[Reg.scala 35:{20,20}]
lfsr_q_14 <= reset | _GEN_14; // @[Reg.scala 35:{20,20}]
lfsr_q_15 <= reset | _GEN_15; // @[Reg.scala 35:{20,20}]
lfsr_q_16 <= reset | _GEN_16; // @[Reg.scala 35:{20,20}]
lfsr_q_17 <= reset | _GEN_17; // @[Reg.scala 35:{20,20}]
lfsr_q_18 <= reset | _GEN_18; // @[Reg.scala 35:{20,20}]
lfsr_q_19 <= reset | _GEN_19; // @[Reg.scala 35:{20,20}]
lfsr_q_20 <= reset | _GEN_20; // @[Reg.scala 35:{20,20}]
lfsr_q_21 <= reset | _GEN_21; // @[Reg.scala 35:{20,20}]
lfsr_q_22 <= reset | _GEN_22; // @[Reg.scala 35:{20,20}]
lfsr_q_23 <= reset | _GEN_23; // @[Reg.scala 35:{20,20}]
end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
lfsr_q_0 = _RAND_0[0:0];
_RAND_1 = {1{`RANDOM}};
lfsr_q_24 = _RAND_1[0:0];
_RAND_2 = {1{`RANDOM}};
lfsr_q_30 = _RAND_2[0:0];
_RAND_3 = {1{`RANDOM}};
lfsr_q_1 = _RAND_3[0:0];
_RAND_4 = {1{`RANDOM}};
lfsr_q_25 = _RAND_4[0:0];
_RAND_5 = {1{`RANDOM}};
lfsr_q_31 = _RAND_5[0:0];
_RAND_6 = {1{`RANDOM}};
lfsr_q_2 = _RAND_6[0:0];
_RAND_7 = {1{`RANDOM}};
lfsr_q_26 = _RAND_7[0:0];
_RAND_8 = {1{`RANDOM}};
lfsr_q_3 = _RAND_8[0:0];
_RAND_9 = {1{`RANDOM}};
lfsr_q_27 = _RAND_9[0:0];
_RAND_10 = {1{`RANDOM}};
lfsr_q_4 = _RAND_10[0:0];
_RAND_11 = {1{`RANDOM}};
lfsr_q_28 = _RAND_11[0:0];
_RAND_12 = {1{`RANDOM}};
lfsr_q_5 = _RAND_12[0:0];
_RAND_13 = {1{`RANDOM}};
lfsr_q_29 = _RAND_13[0:0];
_RAND_14 = {1{`RANDOM}};
lfsr_q_6 = _RAND_14[0:0];
_RAND_15 = {1{`RANDOM}};
lfsr_q_7 = _RAND_15[0:0];
_RAND_16 = {1{`RANDOM}};
lfsr_q_8 = _RAND_16[0:0];
_RAND_17 = {1{`RANDOM}};
lfsr_q_9 = _RAND_17[0:0];
_RAND_18 = {1{`RANDOM}};
lfsr_q_10 = _RAND_18[0:0];
_RAND_19 = {1{`RANDOM}};
lfsr_q_11 = _RAND_19[0:0];
_RAND_20 = {1{`RANDOM}};
lfsr_q_12 = _RAND_20[0:0];
_RAND_21 = {1{`RANDOM}};
lfsr_q_13 = _RAND_21[0:0];
_RAND_22 = {1{`RANDOM}};
lfsr_q_14 = _RAND_22[0:0];
_RAND_23 = {1{`RANDOM}};
lfsr_q_15 = _RAND_23[0:0];
_RAND_24 = {1{`RANDOM}};
lfsr_q_16 = _RAND_24[0:0];
_RAND_25 = {1{`RANDOM}};
lfsr_q_17 = _RAND_25[0:0];
_RAND_26 = {1{`RANDOM}};
lfsr_q_18 = _RAND_26[0:0];
_RAND_27 = {1{`RANDOM}};
lfsr_q_19 = _RAND_27[0:0];
_RAND_28 = {1{`RANDOM}};
lfsr_q_20 = _RAND_28[0:0];
_RAND_29 = {1{`RANDOM}};
lfsr_q_21 = _RAND_29[0:0];
_RAND_30 = {1{`RANDOM}};
lfsr_q_22 = _RAND_30[0:0];
_RAND_31 = {1{`RANDOM}};
lfsr_q_23 = _RAND_31[0:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module CDROut(
input clock,
input reset,
output io_axis_ready,
input io_axis_valid,
input [7:0] io_axis_bits_tdata,
input io_axis_bits_tlast,
input io_axis_bits_tuser,
output io_serDat
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
reg [31:0] _RAND_3;
`endif // RANDOMIZE_REG_INIT
wire crcUnit_clock; // @[CDROut.scala 23:23]
wire crcUnit_reset; // @[CDROut.scala 23:23]
wire crcUnit_io_isEnable; // @[CDROut.scala 23:23]
wire [7:0] crcUnit_io_dataIn; // @[CDROut.scala 23:23]
wire [31:0] crcUnit_io_crc; // @[CDROut.scala 23:23]
reg [1:0] stateCurr; // @[CDROut.scala 35:26]
reg [2:0] bitCnt; // @[CDROut.scala 38:19]
reg [15:0] byteCnt; // @[CDROut.scala 39:20]
wire reset_crc = stateCurr == 2'h0; // @[CDROut.scala 42:29]
wire _crcUnit_io_isEnable_T = io_axis_ready & io_axis_valid; // @[Decoupled.scala 51:35]
reg [7:0] shiftData; // @[CDROut.scala 48:26]
wire _stateNext_T_2 = stateCurr == 2'h1; // @[CDROut.scala 52:16]
wire _stateNext_T_3 = byteCnt == 16'h7; // @[CDROut.scala 52:54]
wire _stateNext_T_4 = bitCnt == 3'h7; // @[CDROut.scala 52:71]
wire [1:0] _stateNext_T_6 = byteCnt == 16'h7 & bitCnt == 3'h7 ? 2'h2 : 2'h1; // @[CDROut.scala 52:44]
wire _stateNext_T_7 = stateCurr == 2'h2; // @[CDROut.scala 53:16]
wire [1:0] _stateNext_T_9 = io_axis_bits_tlast ? 2'h3 : 2'h2; // @[CDROut.scala 53:63]
wire [1:0] _stateNext_T_10 = _crcUnit_io_isEnable_T ? _stateNext_T_9 : 2'h3; // @[CDROut.scala 53:44]
wire _stateNext_T_11 = stateCurr == 2'h3; // @[CDROut.scala 54:16]
wire _stateNext_T_12 = byteCnt == 16'h3; // @[CDROut.scala 54:54]
wire [1:0] _stateNext_T_15 = byteCnt == 16'h3 & _stateNext_T_4 ? 2'h3 : 2'h0; // @[CDROut.scala 54:44]
wire _stateNext_T_16 = reset_crc & io_axis_valid; // @[Mux.scala 27:73]
wire [1:0] _stateNext_T_17 = _stateNext_T_2 ? _stateNext_T_6 : 2'h0; // @[Mux.scala 27:73]
wire [1:0] _stateNext_T_18 = _stateNext_T_7 ? _stateNext_T_10 : 2'h0; // @[Mux.scala 27:73]
wire [1:0] _stateNext_T_19 = _stateNext_T_11 ? _stateNext_T_15 : 2'h0; // @[Mux.scala 27:73]
wire [1:0] _GEN_8 = {{1'd0}, _stateNext_T_16}; // @[Mux.scala 27:73]
wire [1:0] _stateNext_T_20 = _GEN_8 | _stateNext_T_17; // @[Mux.scala 27:73]
wire [1:0] _stateNext_T_21 = _stateNext_T_20 | _stateNext_T_18; // @[Mux.scala 27:73]
wire [1:0] stateNext = _stateNext_T_21 | _stateNext_T_19; // @[Mux.scala 27:73]
wire _io_axis_ready_T_5 = _stateNext_T_2 & _stateNext_T_3 | _stateNext_T_7; // @[CDROut.scala 60:56]
wire [8:0] _shiftData_T = {shiftData, 1'h0}; // @[CDROut.scala 70:30]
wire _shiftData_T_1 = byteCnt == 16'h6; // @[CDROut.scala 74:21]
wire [7:0] _shiftData_T_3 = _stateNext_T_3 ? io_axis_bits_tdata : 8'h55; // @[Mux.scala 101:16]
wire [7:0] _shiftData_T_4 = _shiftData_T_1 ? 8'hd5 : _shiftData_T_3; // @[Mux.scala 101:16]
wire _shiftData_T_5 = byteCnt == 16'h0; // @[CDROut.scala 81:21]
wire [7:0] _shiftData_T_7 = ~crcUnit_io_crc[7:0]; // @[CDROut.scala 81:33]
wire _shiftData_T_8 = byteCnt == 16'h1; // @[CDROut.scala 82:21]
wire [7:0] _shiftData_T_10 = ~crcUnit_io_crc[15:8]; // @[CDROut.scala 82:33]
wire _shiftData_T_11 = byteCnt == 16'h2; // @[CDROut.scala 83:21]
wire [7:0] _shiftData_T_13 = ~crcUnit_io_crc[23:16]; // @[CDROut.scala 83:33]
wire [7:0] _shiftData_T_16 = ~crcUnit_io_crc[31:24]; // @[CDROut.scala 84:33]
wire [7:0] _shiftData_T_17 = _shiftData_T_5 ? _shiftData_T_7 : 8'h0; // @[Mux.scala 27:73]
wire [7:0] _shiftData_T_18 = _shiftData_T_8 ? _shiftData_T_10 : 8'h0; // @[Mux.scala 27:73]
wire [7:0] _shiftData_T_19 = _shiftData_T_11 ? _shiftData_T_13 : 8'h0; // @[Mux.scala 27:73]
wire [7:0] _shiftData_T_20 = _stateNext_T_12 ? _shiftData_T_16 : 8'h0; // @[Mux.scala 27:73]
wire [7:0] _shiftData_T_21 = _shiftData_T_17 | _shiftData_T_18; // @[Mux.scala 27:73]
wire [7:0] _shiftData_T_22 = _shiftData_T_21 | _shiftData_T_19; // @[Mux.scala 27:73]
wire [7:0] _shiftData_T_23 = _shiftData_T_22 | _shiftData_T_20; // @[Mux.scala 27:73]
wire [7:0] _GEN_0 = _stateNext_T_11 ? _shiftData_T_23 : shiftData; // @[CDROut.scala 79:45 80:19 48:26]
wire [7:0] _GEN_1 = _stateNext_T_7 ? io_axis_bits_tdata : _GEN_0; // @[CDROut.scala 77:49 78:19]
wire [7:0] _GEN_2 = _stateNext_T_2 ? _shiftData_T_4 : _GEN_1; // @[CDROut.scala 72:43 73:19]
wire [8:0] _GEN_3 = bitCnt != 3'h7 ? _shiftData_T : {{1'd0}, _GEN_2}; // @[CDROut.scala 69:27 70:17]
wire [8:0] _GEN_4 = reset_crc & stateNext == 2'h1 ? 9'h55 : _GEN_3; // @[CDROut.scala 66:65 67:15]
wire [2:0] _bitCnt_T_1 = bitCnt + 3'h1; // @[CDROut.scala 94:22]
wire [15:0] _byteCnt_T_1 = byteCnt + 16'h1; // @[CDROut.scala 100:24]
wire [8:0] _GEN_9 = reset ? 9'h0 : _GEN_4; // @[CDROut.scala 48:{26,26}]
crc32_8 crcUnit ( // @[CDROut.scala 23:23]
.clock(crcUnit_clock),
.reset(crcUnit_reset),
.io_isEnable(crcUnit_io_isEnable),
.io_dataIn(crcUnit_io_dataIn),
.io_crc(crcUnit_io_crc)
);
assign io_axis_ready = _stateNext_T_4 & _io_axis_ready_T_5; // @[CDROut.scala 59:20]
assign io_serDat = shiftData[7]; // @[CDROut.scala 57:33]
assign crcUnit_clock = clock;
assign crcUnit_reset = reset | reset_crc; // @[CDROut.scala 43:33]
assign crcUnit_io_isEnable = io_axis_ready & io_axis_valid; // @[Decoupled.scala 51:35]
assign crcUnit_io_dataIn = io_axis_bits_tdata; // @[CDROut.scala 45:23]
always @(posedge clock) begin
if (reset) begin // @[CDROut.scala 35:26]
stateCurr <= 2'h0; // @[CDROut.scala 35:26]
end else begin
stateCurr <= stateNext; // @[CDROut.scala 35:26]
end
if (reset_crc) begin // @[CDROut.scala 91:35]
bitCnt <= 3'h0; // @[CDROut.scala 92:12]
end else begin
bitCnt <= _bitCnt_T_1; // @[CDROut.scala 94:12]
end
if (stateNext != stateCurr) begin // @[CDROut.scala 97:34]
byteCnt <= 16'h0; // @[CDROut.scala 98:13]
end else if (_stateNext_T_4) begin // @[CDROut.scala 99:32]
byteCnt <= _byteCnt_T_1; // @[CDROut.scala 100:13]
end
shiftData <= _GEN_9[7:0]; // @[CDROut.scala 48:{26,26}]
end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
stateCurr = _RAND_0[1:0];
_RAND_1 = {1{`RANDOM}};
bitCnt = _RAND_1[2:0];
_RAND_2 = {1{`RANDOM}};
byteCnt = _RAND_2[15:0];
_RAND_3 = {1{`RANDOM}};
shiftData = _RAND_3[7:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule

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tb/cdrOut_tb.v Normal file
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`timescale 1 ns / 1 ps
module CDROut_tb();
reg clock = 0;
reg reset = 1;
wire serDat;
wire axis_ready;
reg axis_valid = 0;
reg [7:0] axis_bits_tdata;
reg axis_bits_tlast;
reg axis_bits_tuser;
CDROut s_CDROut(
.clock(clock),
.reset(reset),
.io_axis_ready(axis_ready),
.io_axis_valid(axis_valid),
.io_axis_bits_tdata(axis_bits_tdata),
.io_axis_bits_tlast(axis_bits_tlast),
.io_axis_bits_tuser(axis_bits_tuser),
.io_serDat(serDat)
);
initial begin
forever #20 clock = ~clock;
end
initial begin
# 100 reset = 1;
# 100 reset = 0;
end
reg [7:0] cnt = 0;
// always @(posedge clock) begin
// if( cnt == 8'd0 ) begin
// #2 axis_valid <= 1'b1;
// #2 axis_bits_tdata <= cnt;
// #2 axis_bits_tlast <= 1'b0;
// #2 axis_bits_tuser <= 1'b0;
// #2 cnt <= cnt + 8'd1;
// end else begin
// if( axis_valid & axis_ready ) begin
// axis_valid <= 1'b0;
// end else if( ~axis_valid ) begin
// #2 axis_valid <= 1'b1;
// if ( cnt == 8'd255 ) begin
// #2 axis_bits_tlast <= 1'b1;
// end else begin
// #2 axis_bits_tlast <= 1'b0;
// #2 cnt <= cnt + 8'd1;
// end
// end
// end
// end
always @(posedge clock) begin
if( cnt == 8'd0 ) begin
#2 axis_valid <= 1'b1;
#2 axis_bits_tdata <= cnt;
#2 axis_bits_tlast <= 1'b0;
#2 axis_bits_tuser <= 1'b0;
#2 cnt <= cnt + 8'd1;
end else begin
if( axis_valid & axis_ready ) begin
if ( axis_bits_tlast ) begin
#2 axis_valid <= 1'b0;
#2 axis_bits_tlast <= 1'b0;
end else begin
#2 axis_bits_tdata <= cnt;
#2 axis_bits_tuser <= 1'b0;
if( cnt == 8'd31 ) begin
#2 axis_bits_tlast <= 1'b1;
end else begin
#2 cnt <= cnt + 8'd1;
end
end
end
end
end
initial begin
# 100000
$finish;
end
initial begin
$dumpfile("./build/wave.vcd"); //生成的vcd文件名称
$dumpvars(0, CDROut_tb);//tb模块名称
end
endmodule