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4倍频采3次

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RuigeLee
2024-09-20 14:55:43 +08:00
parent 1368e9037d
commit 3c357b54e0
2 changed files with 19 additions and 8 deletions
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4
src/main/scala/backBoard/ebus/CDRIn.scala
View File

@@ -23,8 +23,8 @@ abstract class CDRInBase extends Module{
}
trait CDRInOverSample{ this: CDRInBase =>
val sampleReg = withClockAndReset(io.overCLK.asClock, reset.asBool){ ShiftRegisters( RegNext(io.serDat), sampleRate ) }
val arbResult = VecInit(sampleReg).count( (x:Bool) => (x === true.B) ) > (sampleRate / 2).U
val sampleReg = withClockAndReset(io.overCLK.asClock, reset.asBool){ ShiftRegisters( RegNext(io.serDat), sampleRate-1 ) }
val arbResult = VecInit(sampleReg).count( (x:Bool) => (x === true.B) ) > ((sampleRate-1) / 2).U
val syncSerDat = ShiftRegister( arbResult, 2 )
}

23
tb/cdrInOut_tb.v
View File

@@ -72,6 +72,7 @@ initial begin
end
initial begin
#10
forever #20 overCLK = ~overCLK;
end
@@ -81,14 +82,24 @@ initial begin
end
reg [7:0] cnt = 0;
// reg [7:0] cnt = 0;
reg [31:0] rtc_cnt=0;
always @(posedge clock) begin
if( rtc_cnt > 200 ) begin
rtc_cnt <= #2 0;
end else begin
rtc_cnt <= #2 rtc_cnt + 1;
end
end
reg [7:0] cnt;
always @(posedge clock) begin
if( reset ) begin
if( rtc_cnt == 0 ) begin
cnt <= #2 0;
tx_axis_valid <= #2 1'b0;
end else begin
if( cnt == 8'd0 ) begin
tx_axis_valid <= #2 1'b1;
@@ -106,11 +117,11 @@ reg [7:0] cnt = 0;
tx_axis_bits_tuser <= #2 1'b0;
if( cnt == 8'd1 ) begin
tx_axis_bits_tdata <= #2 32;
tx_axis_bits_tdata <= #2 8'h1;
end
if( cnt == 8'd35 ) begin
tx_axis_bits_tlast <= #2 1'b1;
if( cnt == 8'd4 ) begin
tx_axis_bits_tlast <= #2 8'h1;
end else begin
cnt <= #2 cnt + 8'd1;
end