文件结构调整
This commit is contained in:
Ruige Lee
@@ -1,226 +0,0 @@
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package BACK
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import chisel3._
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import chisel3.util._
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import org.chipsalliance.cde.config._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.diplomacy._
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class MirrorSRAMDP extends BlackBox with HasBlackBoxInline {
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class MirrorSRAMDPIO extends Bundle{
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val addrA = Input(UInt(10.W))
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val datawA = Input( UInt(16.W) )
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val datarA = Output( UInt(16.W) )
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val enwA = Input(Bool())
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val enrA = Input(Bool())
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val clockA = Input(Bool())
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val addrB = Input(UInt(10.W))
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val datawB = Input( UInt(16.W) )
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val datarB = Output( UInt(16.W) )
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val enwB = Input(Bool())
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val enrB = Input(Bool())
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val clockB = Input(Bool())
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}
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val io: MirrorSRAMDPIO = IO(new MirrorSRAMDPIO)
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setInline("MirrorSRAMDP.v",
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"""
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| module MirrorSRAMDP(
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| input [15:0] datawA,
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| input [9:0] addrA,
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| input enwA,
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| input enrA,
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| output [15:0] datarA,
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| input clockA,
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| input [15:0] datawB,
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| input [9:0] addrB,
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| input enwB,
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| input enrB,
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| output [15:0] datarB,
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| input clockB
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| );
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| reg [15:0] mem[0:1023];
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| reg [15:0] data_outa_reg = 16'b0;
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| reg [15:0] data_outb_reg = 16'b0;
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| assign datarA = data_outa_reg;
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| assign datarB = data_outb_reg;
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| always@( posedge clockA ) begin
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| if( enrA ) begin
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| end
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| if( enwA ) begin
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| mem[addrA] <= datawA;
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| end else begin
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| data_outa_reg <= mem[addrA];
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| end
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| end
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| always@( posedge clockB ) begin
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| if(enrB) begin
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| end
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| if( enwB ) begin
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| mem[addrB] <= datawB;
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| end else begin
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| data_outb_reg <= mem[addrB];
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| end
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| end
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| initial begin
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| for( integer i = 0; i < 1024; i = i + 1 ) begin
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| mem[i] = $random;
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| end
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| end
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| //Gowin_DPB your_instance_name(
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| // .douta(datarA), //output [15:0] douta
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| // .doutb(datarB), //output [15:0] doutb
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| // .clka(clockA), //input clka
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| // .ocea(1'b1), //input ocea
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| // .cea(1'b1), //input cea
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| // .reseta(1'b0), //input reseta
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| // .wrea(enwA), //input wrea
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| // .clkb(clockB), //input clkb
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| // .oceb(1'b1), //input oceb
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| // .ceb(1'b1), //input ceb
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| // .resetb(1'b0), //input resetb
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| // .wreb(enwB), //input wreb
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| // .ada(addrA), //input [3:0] ada
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| // .dina(datawA), //input [15:0] dina
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| // .adb(addrB), //input [3:0] adb
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| // .dinb(datawB) //input [15:0] dinb
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| //);
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|endmodule
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""".stripMargin)
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}
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class FSMC_Port_Bundle extends Bundle{
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val ADIn = Input(UInt(16.W))
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val ADOut = Output(UInt(16.W))
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val ADOEn = Output(Bool())
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val csn = Input(Bool())
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val rdn = Input(Bool())
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val wrn = Input(Bool())
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val advn = Input(Bool())
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}
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class FSMC2TileLink(implicit p: Parameters) extends LazyModule{
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val fsmcDev = new SimpleDevice("FSMC", Nil)
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val fsmcNode = TLManagerNode(Seq(TLSlavePortParameters.v1(
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managers = Seq(
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TLSlaveParameters.v2(
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address = Seq(AddressSet(0x10010000L, 0xffffL)), //64K
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name = Some("FSMC"),
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regionType = RegionType.VOLATILE,
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resources = fsmcDev.reg,
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executable = false,
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fifoId = Some(0),
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supports = TLMasterToSlaveTransferSizes(
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get = TransferSizes(1, 32/8),
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putFull = TransferSizes(1, 32/8),
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// putPartial = TransferSizes(1, 32/8),
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),
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)
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),
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beatBytes = 32/8)))
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lazy val module = new Impl
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class Impl extends LazyModuleImp(this) {
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val io = IO(new FSMC_Port_Bundle)
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val ( fsmc_bus, fsmc_edge ) = fsmcNode.in.head
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val sram = Module(new MirrorSRAMDP())
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assert( ~(sram.io.enwA & sram.io.enrA) )
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assert( ~(sram.io.enwB & sram.io.enrB) )
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sram.io.clockA := clock.asBool //system
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sram.io.clockB := clock.asBool //system
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io.ADOEn := ~io.rdn & ~io.csn & io.advn
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val latchAddr = RegEnable( io.ADIn, ~io.advn & ~io.csn)
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val activeAddr = latchAddr(9,0)
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sram.io.addrA := activeAddr
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sram.io.datawA := io.ADIn
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sram.io.enwA := ~io.csn & ~io.wrn
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sram.io.enrA := ~io.csn & ~io.rdn
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io.ADOut := sram.io.datarA
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sram.io.addrB := fsmc_bus.a.bits.address
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sram.io.datawB := fsmc_bus.a.bits.data
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sram.io.enwB := fsmc_bus.a.fire & (fsmc_bus.a.bits.opcode === 0.U | fsmc_bus.a.bits.opcode === 1.U)
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sram.io.enrB := fsmc_bus.a.fire & (fsmc_bus.a.bits.opcode === 4.U)
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val tlAReady = RegInit(true.B)
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val tlaInfo = Reg(new TLBundleA(fsmc_edge.bundle))
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val tlDValid = RegInit(false.B)
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val isRead = tlaInfo.opcode === 4.U
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when( fsmc_bus.a.fire ) {
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tlaInfo := fsmc_bus.a.bits
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}
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fsmc_bus.a.ready := tlAReady
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fsmc_bus.d.valid := tlDValid
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when( fsmc_bus.a.fire ){
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tlAReady := false.B
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} .elsewhen( fsmc_bus.d.fire ) {
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tlAReady := true.B
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}
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when( RegNext(fsmc_bus.a.fire) ){
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tlDValid := true.B
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} .elsewhen( fsmc_bus.d.fire ) {
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tlDValid := false.B
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}
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when(isRead) {
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fsmc_bus.d.bits := fsmc_edge.AccessAck(tlaInfo, sram.io.datarB)
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} .otherwise {
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fsmc_bus.d.bits := fsmc_edge.AccessAck(tlaInfo)
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}
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}
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}
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@@ -59,14 +59,14 @@ object testModule extends App {
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// ))
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val cfg = new BackCfg
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// val cfg = new BackCfg
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(new chisel3.stage.ChiselStage).execute( Array("--gen-mem-verilog", "true", "--show-registrations", "--full-stacktrace", "--target-dir", "generated/cdr/", "-e", "verilog") ++ args, Seq(
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ChiselGeneratorAnnotation(() => {
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val soc = LazyModule(new BackSys()(cfg))
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soc.module
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})
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))
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// (new chisel3.stage.ChiselStage).execute( Array("--gen-mem-verilog", "true", "--show-registrations", "--full-stacktrace", "--target-dir", "generated/cdr/", "-e", "verilog") ++ args, Seq(
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// ChiselGeneratorAnnotation(() => {
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// val soc = LazyModule(new BackSys()(cfg))
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// soc.module
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// })
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// ))
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// (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
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