From ea6ea66040371157ba8190b7c2da160ffa5959b7 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Wed, 26 Feb 2025 15:36:57 +0800 Subject: [PATCH] =?UTF-8?q?=E6=96=87=E4=BB=B6=E7=BB=93=E6=9E=84=E8=B0=83?= =?UTF-8?q?=E6=95=B4?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../scala/backBoard/ebus/FSMC2TileLink.scala | 226 ------------------ .../{BackSystem.scala => BackSystem.scala.bk} | 0 ...corv32_mem.scala => Picorv32_mem.scala.bk} | 0 ...Picorv32_tl.scala => Picorv32_tl.scala.bk} | 0 .../{SimpleGpio.scala => SimpleGpio.scala.bk} | 0 .../{SimpleSRAM.scala => SimpleSRAM.scala.bk} | 0 .../pico/{TLCDR.scala => TLCDR.scala.bk} | 0 .../{picorv32.scala => picorv32.scala.bk} | 0 src/test/scala/gcd/test.scala | 14 +- 9 files changed, 7 insertions(+), 233 deletions(-) delete mode 100644 src/main/scala/backBoard/ebus/FSMC2TileLink.scala rename src/main/scala/backBoard/pico/{BackSystem.scala => BackSystem.scala.bk} (100%) rename src/main/scala/backBoard/pico/{Picorv32_mem.scala => Picorv32_mem.scala.bk} (100%) rename src/main/scala/backBoard/pico/{Picorv32_tl.scala => Picorv32_tl.scala.bk} (100%) rename src/main/scala/backBoard/pico/{SimpleGpio.scala => SimpleGpio.scala.bk} (100%) rename src/main/scala/backBoard/pico/{SimpleSRAM.scala => SimpleSRAM.scala.bk} (100%) rename src/main/scala/backBoard/pico/{TLCDR.scala => TLCDR.scala.bk} (100%) rename src/main/scala/backBoard/pico/{picorv32.scala => picorv32.scala.bk} (100%) diff --git a/src/main/scala/backBoard/ebus/FSMC2TileLink.scala b/src/main/scala/backBoard/ebus/FSMC2TileLink.scala deleted file mode 100644 index d14b1b4..0000000 --- a/src/main/scala/backBoard/ebus/FSMC2TileLink.scala +++ /dev/null @@ -1,226 +0,0 @@ -package BACK - -import chisel3._ -import chisel3.util._ - -import org.chipsalliance.cde.config._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.diplomacy._ - - -class MirrorSRAMDP extends BlackBox with HasBlackBoxInline { - - class MirrorSRAMDPIO extends Bundle{ - - val addrA = Input(UInt(10.W)) - val datawA = Input( UInt(16.W) ) - val datarA = Output( UInt(16.W) ) - val enwA = Input(Bool()) - val enrA = Input(Bool()) - val clockA = Input(Bool()) - - - val addrB = Input(UInt(10.W)) - val datawB = Input( UInt(16.W) ) - val datarB = Output( UInt(16.W) ) - val enwB = Input(Bool()) - val enrB = Input(Bool()) - val clockB = Input(Bool()) - - } - val io: MirrorSRAMDPIO = IO(new MirrorSRAMDPIO) - - setInline("MirrorSRAMDP.v", - """ - | module MirrorSRAMDP( - | input [15:0] datawA, - | input [9:0] addrA, - | input enwA, - | input enrA, - | output [15:0] datarA, - | input clockA, - | - | input [15:0] datawB, - | input [9:0] addrB, - | input enwB, - | input enrB, - | output [15:0] datarB, - | input clockB - | ); - | - | reg [15:0] mem[0:1023]; - | reg [15:0] data_outa_reg = 16'b0; - | reg [15:0] data_outb_reg = 16'b0; - | - | assign datarA = data_outa_reg; - | assign datarB = data_outb_reg; - | - | always@( posedge clockA ) begin - | if( enrA ) begin - | end - | - | if( enwA ) begin - | mem[addrA] <= datawA; - | end else begin - | data_outa_reg <= mem[addrA]; - | end - | end - | - | - | always@( posedge clockB ) begin - | if(enrB) begin - | end - | - | if( enwB ) begin - | mem[addrB] <= datawB; - | end else begin - | data_outb_reg <= mem[addrB]; - | end - | end - | - | initial begin - | for( integer i = 0; i < 1024; i = i + 1 ) begin - | mem[i] = $random; - | end - | end - | - | //Gowin_DPB your_instance_name( - | // .douta(datarA), //output [15:0] douta - | // .doutb(datarB), //output [15:0] doutb - | // .clka(clockA), //input clka - | // .ocea(1'b1), //input ocea - | // .cea(1'b1), //input cea - | // .reseta(1'b0), //input reseta - | // .wrea(enwA), //input wrea - | // .clkb(clockB), //input clkb - | // .oceb(1'b1), //input oceb - | // .ceb(1'b1), //input ceb - | // .resetb(1'b0), //input resetb - | // .wreb(enwB), //input wreb - | // .ada(addrA), //input [3:0] ada - | // .dina(datawA), //input [15:0] dina - | // .adb(addrB), //input [3:0] adb - | // .dinb(datawB) //input [15:0] dinb - | //); - | - |endmodule - """.stripMargin) -} - - - - - - - - - - - - -class FSMC_Port_Bundle extends Bundle{ - - val ADIn = Input(UInt(16.W)) - val ADOut = Output(UInt(16.W)) - val ADOEn = Output(Bool()) - val csn = Input(Bool()) - val rdn = Input(Bool()) - val wrn = Input(Bool()) - val advn = Input(Bool()) -} - - - -class FSMC2TileLink(implicit p: Parameters) extends LazyModule{ - - val fsmcDev = new SimpleDevice("FSMC", Nil) - val fsmcNode = TLManagerNode(Seq(TLSlavePortParameters.v1( - managers = Seq( - TLSlaveParameters.v2( - address = Seq(AddressSet(0x10010000L, 0xffffL)), //64K - name = Some("FSMC"), - regionType = RegionType.VOLATILE, - resources = fsmcDev.reg, - executable = false, - fifoId = Some(0), - supports = TLMasterToSlaveTransferSizes( - get = TransferSizes(1, 32/8), - putFull = TransferSizes(1, 32/8), - // putPartial = TransferSizes(1, 32/8), - ), - ) - ), - beatBytes = 32/8))) - - - - lazy val module = new Impl - - class Impl extends LazyModuleImp(this) { - val io = IO(new FSMC_Port_Bundle) - - val ( fsmc_bus, fsmc_edge ) = fsmcNode.in.head - - val sram = Module(new MirrorSRAMDP()) - assert( ~(sram.io.enwA & sram.io.enrA) ) - assert( ~(sram.io.enwB & sram.io.enrB) ) - sram.io.clockA := clock.asBool //system - sram.io.clockB := clock.asBool //system - - io.ADOEn := ~io.rdn & ~io.csn & io.advn - val latchAddr = RegEnable( io.ADIn, ~io.advn & ~io.csn) - val activeAddr = latchAddr(9,0) - - sram.io.addrA := activeAddr - sram.io.datawA := io.ADIn - sram.io.enwA := ~io.csn & ~io.wrn - sram.io.enrA := ~io.csn & ~io.rdn - io.ADOut := sram.io.datarA - - - - - sram.io.addrB := fsmc_bus.a.bits.address - sram.io.datawB := fsmc_bus.a.bits.data - sram.io.enwB := fsmc_bus.a.fire & (fsmc_bus.a.bits.opcode === 0.U | fsmc_bus.a.bits.opcode === 1.U) - sram.io.enrB := fsmc_bus.a.fire & (fsmc_bus.a.bits.opcode === 4.U) - - - val tlAReady = RegInit(true.B) - val tlaInfo = Reg(new TLBundleA(fsmc_edge.bundle)) - val tlDValid = RegInit(false.B) - val isRead = tlaInfo.opcode === 4.U - - when( fsmc_bus.a.fire ) { - tlaInfo := fsmc_bus.a.bits - } - - fsmc_bus.a.ready := tlAReady - fsmc_bus.d.valid := tlDValid - - when( fsmc_bus.a.fire ){ - tlAReady := false.B - } .elsewhen( fsmc_bus.d.fire ) { - tlAReady := true.B - } - - - when( RegNext(fsmc_bus.a.fire) ){ - tlDValid := true.B - } .elsewhen( fsmc_bus.d.fire ) { - tlDValid := false.B - } - - when(isRead) { - fsmc_bus.d.bits := fsmc_edge.AccessAck(tlaInfo, sram.io.datarB) - } .otherwise { - fsmc_bus.d.bits := fsmc_edge.AccessAck(tlaInfo) - } - - - - - - - } -} diff --git a/src/main/scala/backBoard/pico/BackSystem.scala b/src/main/scala/backBoard/pico/BackSystem.scala.bk similarity index 100% rename from src/main/scala/backBoard/pico/BackSystem.scala rename to src/main/scala/backBoard/pico/BackSystem.scala.bk diff --git a/src/main/scala/backBoard/pico/Picorv32_mem.scala b/src/main/scala/backBoard/pico/Picorv32_mem.scala.bk similarity index 100% rename from src/main/scala/backBoard/pico/Picorv32_mem.scala rename to src/main/scala/backBoard/pico/Picorv32_mem.scala.bk diff --git a/src/main/scala/backBoard/pico/Picorv32_tl.scala b/src/main/scala/backBoard/pico/Picorv32_tl.scala.bk similarity index 100% rename from src/main/scala/backBoard/pico/Picorv32_tl.scala rename to src/main/scala/backBoard/pico/Picorv32_tl.scala.bk diff --git a/src/main/scala/backBoard/pico/SimpleGpio.scala b/src/main/scala/backBoard/pico/SimpleGpio.scala.bk similarity index 100% rename from src/main/scala/backBoard/pico/SimpleGpio.scala rename to src/main/scala/backBoard/pico/SimpleGpio.scala.bk diff --git a/src/main/scala/backBoard/pico/SimpleSRAM.scala b/src/main/scala/backBoard/pico/SimpleSRAM.scala.bk similarity index 100% rename from src/main/scala/backBoard/pico/SimpleSRAM.scala rename to src/main/scala/backBoard/pico/SimpleSRAM.scala.bk diff --git a/src/main/scala/backBoard/pico/TLCDR.scala b/src/main/scala/backBoard/pico/TLCDR.scala.bk similarity index 100% rename from src/main/scala/backBoard/pico/TLCDR.scala rename to src/main/scala/backBoard/pico/TLCDR.scala.bk diff --git a/src/main/scala/backBoard/pico/picorv32.scala b/src/main/scala/backBoard/pico/picorv32.scala.bk similarity index 100% rename from src/main/scala/backBoard/pico/picorv32.scala rename to src/main/scala/backBoard/pico/picorv32.scala.bk diff --git a/src/test/scala/gcd/test.scala b/src/test/scala/gcd/test.scala index 40843a0..f1c13fb 100644 --- a/src/test/scala/gcd/test.scala +++ b/src/test/scala/gcd/test.scala @@ -59,14 +59,14 @@ object testModule extends App { // )) - val cfg = new BackCfg + // val cfg = new BackCfg - (new chisel3.stage.ChiselStage).execute( Array("--gen-mem-verilog", "true", "--show-registrations", "--full-stacktrace", "--target-dir", "generated/cdr/", "-e", "verilog") ++ args, Seq( - ChiselGeneratorAnnotation(() => { - val soc = LazyModule(new BackSys()(cfg)) - soc.module - }) - )) + // (new chisel3.stage.ChiselStage).execute( Array("--gen-mem-verilog", "true", "--show-registrations", "--full-stacktrace", "--target-dir", "generated/cdr/", "-e", "verilog") ++ args, Seq( + // ChiselGeneratorAnnotation(() => { + // val soc = LazyModule(new BackSys()(cfg)) + // soc.module + // }) + // )) // (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(