RuigeLee
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692188fa2f
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单双边沿切换 类模式
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2025-09-22 16:34:53 +08:00 |
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RuigeLee
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9a93481b68
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修复aqspi读操作时间点
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2025-09-19 17:17:51 +08:00 |
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RuigeLee
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e45f407a1d
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修改dataw_async的更新策略
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2025-09-19 16:19:53 +08:00 |
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RuigeLee
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61897a3dd0
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修正
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2025-09-19 15:50:54 +08:00 |
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RuigeLee
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9b48306396
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更新时序SPI
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2025-09-19 15:41:02 +08:00 |
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RuigeLee
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9fdd360854
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更新慢速qspi
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2025-09-19 14:26:54 +08:00 |
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RuigeLee
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2e19a95b92
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建立双边沿采样Flip-Flop底层逻辑
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2025-09-18 17:55:50 +08:00 |
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RuigeLee
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fb26a40061
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修复同步QSPI使用csn异步复位
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2025-09-18 15:23:57 +08:00 |
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RuigeLee
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a70cfbce8f
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qSpi使用不同边沿采样
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2025-09-18 15:23:11 +08:00 |
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0569733c44
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Merge branch 'mp_eb_dev' into new_spi
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2025-09-17 21:58:01 +08:00 |
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RuigeLee
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759218b570
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修复微调方向
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2025-09-17 17:29:19 +08:00 |
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RuigeLee
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1e2fa0931d
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编译通过
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2025-09-17 11:07:34 +08:00 |
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RuigeLee
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21ffc1b58d
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spi跨时钟域
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2025-09-16 18:01:14 +08:00 |
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RuigeLee
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1dee4519bb
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增加同步子报文A；验证关注点1）变化增量的正负方向 2）deltafinal修正前后跨越正负 3）前仿真的综合行为
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2025-09-16 11:27:02 +08:00 |
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RuigeLee
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e83ba629b7
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优化cdrsim模式
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2025-09-15 17:47:31 +08:00 |
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RuigeLee
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2ecb547bc8
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增加初版CDRIn方案
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2025-09-15 15:31:39 +08:00 |
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RuigeLee
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958987ff6d
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参数化cdrInSample，支持4相位
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2025-09-11 18:57:58 +08:00 |
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RuigeLee
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99b9d9a72f
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修复CDRIn的异步复位
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2025-09-11 18:56:13 +08:00 |
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RuigeLee
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f42c9044d8
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添加分频io
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2025-09-11 15:50:38 +08:00 |
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RuigeLee
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ea7d91e9d3
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检回编译文件
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2025-09-11 15:15:47 +08:00 |
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RuigeLee
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26367fd63c
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删除其它项目设计文件
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2025-09-11 14:30:08 +08:00 |
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RuigeLee
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a24abbc098
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回滚修改
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2025-09-11 14:11:40 +08:00 |
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RuigeLee
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d46e06d5b0
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代码整理
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2025-09-11 11:50:58 +08:00 |
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RuigeLee
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2969cf70a1
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取消3个寄存器只能配置一次的特性
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2025-09-11 11:28:05 +08:00 |
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RuigeLee
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68f3c2ac89
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仅当sm为空时方可修改sm的触发长度，注意cnt=cPtr-rPtr，之前可能wPtr已经移动（可能撤销）
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2025-09-11 11:01:50 +08:00 |
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RuigeLee
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f700b11e84
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latch使用主站offset校准后时间
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2025-09-10 09:12:52 +08:00 |
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RuigeLee
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e258cd4a6c
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优化spi，更严谨
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2025-09-09 18:06:14 +08:00 |
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Ruige
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ba04725e72
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Revert "尝试跨时钟域QSPI，失败"
This reverts commit 5ccf101648.
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2025-09-09 17:50:22 +08:00 |
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RuigeLee
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5ccf101648
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尝试跨时钟域QSPI，失败
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2025-09-09 17:48:52 +08:00 |
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RuigeLee
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22cc6ef0b8
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微调spi访存时间点，提高理论极限频率
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2025-09-09 16:10:19 +08:00 |
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RuigeLee
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a6a546a0f9
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完成对4b5b，8b10b的覆盖测试
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2025-09-08 21:49:56 +08:00 |
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RuigeLee
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561f394b16
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sReg.isLVDSWriteAble 锁定lvds写入syncPoint和synccfg
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2025-09-08 17:48:08 +08:00 |
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RuigeLee
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1d5a257b58
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Merge branch 'mp_eb_dev' into feature/syncSpi
# Conflicts:
# src/main/scala/backBoard/shin/SpiInterface.scala
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2025-09-08 17:07:10 +08:00 |
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RuigeLee
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c3c3a25e77
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修复spicmd没有在每次传输前后复位地问题，或许将导致三态门状态错误
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2025-09-08 17:02:43 +08:00 |
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RuigeLee
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777ca7319b
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修复合并过程中位宽错误
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2025-09-07 22:35:32 +08:00 |
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RuigeLee
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4a21e4b2ba
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修复接线错误
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2025-09-06 23:02:10 +08:00 |
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RuigeLee
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ff7aba38ad
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拆分CDRIn为采样部分和axis部分；调整层次结构，仅将cdrInSample放在顶层；放置3组CDRInSample，使用寄存器选择
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2025-09-06 11:07:41 +08:00 |
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RuigeLee
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ac118289b2
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修复语法错误
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2025-09-05 19:30:35 +08:00 |
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RuigeLee
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4bc5e2927e
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修改key策略
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2025-09-05 17:15:04 +08:00 |
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RuigeLee
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d5523eaa46
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Merge branch 'feature/clk3_shift_allow' into mp_eb_dev
# Conflicts:
# src/main/scala/backBoard/ebus/CDRIn.scala
# tb/shinTest/ShinTopSpiTb.v
# tb/shinTest/gen_pkt.py
# tb/shinTest/testcase/base.py
# tb/shinTest/testcase/environment.py
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2025-09-05 16:01:52 +08:00 |
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RuigeLee
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7ec88aa3a7
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Merge branch 'feature/8b10b' into mp_eb_dev
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2025-09-05 15:43:02 +08:00 |
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RuigeLee
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7b3b4c010d
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8B10B正负相写反
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2025-09-05 15:39:17 +08:00 |
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RuigeLee
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e9bc1d1e18
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cdrin的preamble连续监控10个cycle
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2025-09-05 15:09:52 +08:00 |
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RuigeLee
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adb1d9c1c8
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4b5b 8b10b接线完成
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2025-09-05 12:55:32 +08:00 |
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RuigeLee
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26344d60cd
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写完编解码模块
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2025-09-05 11:11:01 +08:00 |
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RuigeLee
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b1825607ab
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修复中断丢脉冲问题，但每次脉冲宽度比设置多一拍
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2025-09-05 09:58:43 +08:00 |
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RuigeLee
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f609945a6a
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8b10b编码完成
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2025-09-05 09:35:29 +08:00 |
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RuigeLee
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8a29acf4b8
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require是多余约束
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2025-09-04 16:40:07 +08:00 |
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RuigeLee
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4dd1841921
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cPtr需要同步复位
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2025-09-04 16:33:24 +08:00 |
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RuigeLee
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0b7bd505ba
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b5b6编码表
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2025-09-04 16:25:54 +08:00 |
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