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Merge branch 'feature/clk3_shift_allow' into mp_eb_dev

Browse Source 
# Conflicts:
#	src/main/scala/backBoard/ebus/CDRIn.scala
#	tb/shinTest/ShinTopSpiTb.v
#	tb/shinTest/gen_pkt.py
#	tb/shinTest/testcase/base.py
#	tb/shinTest/testcase/environment.py
This commit is contained in:
RuigeLee
2025-09-05 16:01:52 +08:00
parent a21d6eaf54 7ec88aa3a7
commit d5523eaa46
61 changed files with 2510 additions and 605 deletions
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41
src/main/scala/backBoard/ebus/CDRIn.scala
View File

@@ -4,19 +4,24 @@ import chisel3._
import chisel3.util._
//work in 100MHZ
class CDRInIO extends Bundle{
val axis = Decoupled(new AXIS_Bundle(8))
val decode = Flipped(new Decode_Bundle)
val serDat = Input(Bool())
val flush = Input(Bool())
}
abstract class CDRInBase extends Module with RequireAsyncReset{
val io: CDRInIO = IO(new CDRInIO)
io.decode.dataIn := 0.U
val syncSerDat = Wire(Bool())
}
@@ -36,7 +41,7 @@ trait CDRInMultiSample{ this: CDRInBase =>
dontTouch(sampleReg)
for( i <- 0 until clkNum ) {
sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2 ) }
sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2, false.B, true.B ) }
}
val sampleReg_sync = for( i <- 0 until clkNum ) yield {
@@ -91,9 +96,9 @@ trait CDRInMultiSample{ this: CDRInBase =>
}
for( i <- 0 until (8*clkNum)-2 ) {dontTouch(flitReg(i))}
val clearCnt = Reg(UInt(4.W))
val checkCnt = Reg(UInt(4.W))
val arbCali = Reg(UInt( (log2Ceil(8*clkNum)).W ))
val clearCnt = RegInit(0.U(4.W))
val checkCnt = RegInit(0.U(4.W))
val arbCali = RegInit(0.U( (log2Ceil(2*clkNum)).W ))
val isLock = RegInit(false.B)
when( (7*clkNum until 8*clkNum).map{ i => sampleReg_Align(i)}.reduce(_|_) === false.B ){
@@ -201,8 +206,8 @@ trait CDRInAxis{ this: CDRInBase =>
def HeaderByte: Int = 4
val ETH_PRE = "b1100010001".U(10.W)
val ETH_SFD = "b0110100111".U(10.W)
val ETH_PRE = "h68".U(8.W)
val ETH_SFD = "h25".U(8.W)
val STATE_IDLE = 0.U
val STATE_HEADER = 1.U
@@ -211,18 +216,20 @@ trait CDRInAxis{ this: CDRInBase =>
val stateNext = Wire(UInt(2.W))
val stateCurr = RegNext( stateNext, STATE_IDLE )
val bitCnt = Reg(UInt(4.W))
val bitCnt = RegInit(0.U(4.W))
val byteCnt = RegInit(0.U((12+1).W))
val checkSFD = RegInit( 0.U(20.W) )
val checkSFD = RegInit( 0.U(10.W) )
when( io.flush ){
checkSFD := 0.U
} .otherwise{
checkSFD := Cat( checkSFD(18,0), syncSerDat )
checkSFD := Cat( checkSFD(8,0), syncSerDat )
}
val shiftData = Dualb4b5Decoder(checkSFD(9,0))
io.decode.dataIn := checkSFD(9,0)
val shiftData = io.decode.dataOut
val shiftData10Next = ShiftRegister( shiftData, 10, 0.U(8.W), true.B )
val payloadLen = RegInit(0.U(12.W))
@@ -237,7 +244,7 @@ trait CDRInAxis{ this: CDRInBase =>
stateNext :=
Mux( io.flush, STATE_IDLE,
Mux1H(Seq(
(stateCurr === STATE_IDLE) -> ( Mux( checkSFD === Cat(ETH_PRE , ETH_SFD), STATE_HEADER, STATE_IDLE )), //IDLE
(stateCurr === STATE_IDLE) -> ( Mux( shiftData10Next === ETH_PRE && shiftData === ETH_SFD , STATE_HEADER, STATE_IDLE )), //IDLE
(stateCurr === STATE_HEADER) -> ( Mux( (byteCnt === (HeaderByte-1).U) & (bitCnt === 9.U), STATE_PAYLOAD, STATE_HEADER ) ),
(stateCurr === STATE_PAYLOAD) -> ( Mux( (byteCnt === (payloadLen + (4 - 1).U) ) & (bitCnt === 9.U), STATE_IDLE, STATE_PAYLOAD )), // PAYLOAD
)) //crc
@@ -247,7 +254,7 @@ trait CDRInAxis{ this: CDRInBase =>
when( stateCurr === STATE_IDLE & ( checkSFD === Cat(ETH_PRE, ETH_SFD) ) ){ //first align
when( stateCurr === STATE_IDLE & ( shiftData10Next === ETH_PRE && shiftData === ETH_SFD ) ){ //first align
bitCnt := 0.U
} .otherwise{
when( bitCnt === 9.U ){
@@ -259,7 +266,7 @@ trait CDRInAxis{ this: CDRInBase =>
when( io.flush ){
byteCnt := 0.U
} .elsewhen( stateCurr === STATE_IDLE & ( checkSFD === Cat(ETH_PRE, ETH_SFD) ) ){ //first align
} .elsewhen( stateCurr === STATE_IDLE & ( shiftData10Next === ETH_PRE && shiftData === ETH_SFD ) ){ //first align
byteCnt := 0.U
} .elsewhen( bitCnt === 9.U ){
when( stateCurr === STATE_HEADER ){
@@ -276,7 +283,7 @@ trait CDRInAxis{ this: CDRInBase =>
val axis_valid = RegInit(false.B)
val axis_tdata = RegEnable( shiftData, bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) )
val axis_tdata = RegEnable( shiftData, 0.U(8.W), bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) )
val axis_tuser = false.B
val axis_tlast = RegInit( false.B )

34
src/main/scala/backBoard/ebus/CDROut.scala
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@@ -9,14 +9,20 @@ class AXIS_Bundle(dw: Int) extends Bundle{
val tuser = Bool()
}
//work in 100MHZ
class CDROutIO extends Bundle{
val axis = Flipped(Decoupled(new AXIS_Bundle(8)))
val axis = Flipped(Decoupled(new AXIS_Bundle(8)))
val encode = Flipped(new Encode_Bundle)
val serDat = Output(Bool())
val flush = Input(Bool())
}
@@ -29,17 +35,19 @@ class CDROut extends Module with RequireAsyncReset{
def STATE_PREAMBLE = 1.U
def STATE_PAYLOAD = 2.U
val ETH_PRE = "b1100010001".U(10.W)
val ETH_SFD = "b0110100111".U(10.W)
val ETH_PRE = "h68".U(8.W)
val ETH_SFD = "h25".U(8.W)
val stateNext = Wire(UInt(2.W))
val stateCurr = RegNext( stateNext, 0.U )
val bitCnt = Reg(UInt(4.W))
val byteCnt = Reg(UInt(3.W)) //payload dont need to count
val bitCnt = RegInit(0.U(4.W))
val byteCnt = RegInit(0.U(3.W)) //payload dont need to count
val shiftData = RegInit(0.U(10.W))
io.encode.isEnable := false.B //组合逻辑
io.encode.dataIn := 0.U //组合逻辑
stateNext :=
Mux( io.flush, STATE_IDLE,
@@ -65,18 +73,24 @@ class CDROut extends Module with RequireAsyncReset{
when( io.flush ){
shiftData := 0.U
} .elsewhen( stateCurr === STATE_IDLE & stateNext === STATE_PREAMBLE){ //PRE
shiftData := ETH_PRE
shiftData := io.encode.dataOut
io.encode.dataIn := ETH_PRE //组合逻辑
io.encode.isEnable := true.B //组合逻辑
} .otherwise{
when( bitCnt =/= 9.U ){
shiftData := shiftData << 1
} .otherwise{ //bitCnt === 9.U
when( stateCurr === STATE_PREAMBLE ){
shiftData := MuxCase( ETH_PRE, Array(
shiftData := io.encode.dataOut
io.encode.dataIn := MuxCase( ETH_PRE, Array(
( byteCnt === (PRE_NUM-2).U ) -> ETH_SFD,
( byteCnt === (PRE_NUM-1).U ) -> Dualb4b5Encoder(io.axis.bits.tdata),
))
( byteCnt === (PRE_NUM-1).U ) -> io.axis.bits.tdata,
)) //组合逻辑
io.encode.isEnable := true.B //组合逻辑
} .elsewhen( stateCurr === STATE_PAYLOAD ){
shiftData := Dualb4b5Encoder(io.axis.bits.tdata)
io.encode.dataIn := io.axis.bits.tdata //组合逻辑
shiftData := io.encode.dataOut
io.encode.isEnable := true.B //组合逻辑
}
}
}

2
src/main/scala/backBoard/ebus/Encryptor.scala
View File

@@ -13,7 +13,7 @@ class Encryptor_IO_Bundle extends Bundle{
class Encryptor extends Module{
val io: Encryptor_IO_Bundle = IO(new Encryptor_IO_Bundle)
val encryptReg = Reg(UInt(128.W))
val encryptReg = RegInit(0.U(128.W))
when( io.init.valid ){
encryptReg := io.init.bits

13
src/main/scala/backBoard/ebus/b4b5.scala
View File

@@ -63,3 +63,16 @@ object Dualb4b5Decoder{
Cat( b4b5Decoder(enq(9,5)), b4b5Decoder(enq(4,0)) )
}
}
class b4b5DualEncode extends Module with RequireAsyncReset{
val io = IO(new Encode_Bundle)
io.dataOut := Dualb4b5Encoder(io.dataIn)
}
class b4b5DualDecode extends Module with RequireAsyncReset{
val io = IO(new Decode_Bundle)
io.dataOut := Dualb4b5Decoder(io.dataIn)
}

190
src/main/scala/backBoard/ebus/b8b10.scala Normal file
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@@ -0,0 +1,190 @@
package BACK
import chisel3._
import chisel3.util._
class Encode_Bundle extends Bundle{
val dataIn = Input(UInt(8.W))
val isEnable = Input(Bool())
val dataOut = Output(UInt(10.W))
}
class Decode_Bundle extends Bundle{
val dataIn = Input(UInt(10.W))
val dataOut = Output(UInt(8.W))
}
class b8b10Encode extends Module with RequireAsyncReset{
val io = IO(new Encode_Bundle)
val rd = RegInit(false.B)
val b5b6LookUp = Mux1H(Seq(
(io.dataIn(4,0) === "b00000".U) -> Mux( ~rd, "b100111".U(6.W), "b011000".U(6.W) ),
(io.dataIn(4,0) === "b00001".U) -> Mux( ~rd, "b011101".U(6.W), "b100010".U(6.W) ),
(io.dataIn(4,0) === "b00010".U) -> Mux( ~rd, "b101101".U(6.W), "b010010".U(6.W) ),
(io.dataIn(4,0) === "b00011".U) -> "b110001".U(6.W),
(io.dataIn(4,0) === "b00100".U) -> Mux( ~rd, "b110101".U(6.W), "b001010".U(6.W) ),
(io.dataIn(4,0) === "b00101".U) -> "b101001".U(6.W),
(io.dataIn(4,0) === "b00110".U) -> "b011001".U(6.W),
(io.dataIn(4,0) === "b00111".U) -> Mux( ~rd, "b111000".U(6.W), "b000111".U(6.W) ),
(io.dataIn(4,0) === "b01000".U) -> Mux( ~rd, "b111001".U(6.W), "b000110".U(6.W) ),
(io.dataIn(4,0) === "b01001".U) -> "b100101".U(6.W),
(io.dataIn(4,0) === "b01010".U) -> "b010101".U(6.W),
(io.dataIn(4,0) === "b01011".U) -> "b110100".U(6.W),
(io.dataIn(4,0) === "b01100".U) -> "b001101".U(6.W),
(io.dataIn(4,0) === "b01101".U) -> "b101100".U(6.W),
(io.dataIn(4,0) === "b01110".U) -> "b011100".U(6.W),
(io.dataIn(4,0) === "b01111".U) -> Mux( ~rd, "b010111".U(6.W), "b101000".U(6.W) ),
(io.dataIn(4,0) === "b10000".U) -> Mux( ~rd, "b011011".U(6.W), "b100100".U(6.W) ),
(io.dataIn(4,0) === "b10001".U) -> "b100011".U(6.W),
(io.dataIn(4,0) === "b10010".U) -> "b010011".U(6.W),
(io.dataIn(4,0) === "b10011".U) -> "b110010".U(6.W),
(io.dataIn(4,0) === "b10100".U) -> "b001011".U(6.W),
(io.dataIn(4,0) === "b10101".U) -> "b101010".U(6.W),
(io.dataIn(4,0) === "b10110".U) -> "b011010".U(6.W),
(io.dataIn(4,0) === "b10111".U) -> Mux( ~rd, "b111010".U(6.W), "b000101".U(6.W) ),
(io.dataIn(4,0) === "b11000".U) -> Mux( ~rd, "b110011".U(6.W), "b001100".U(6.W) ),
(io.dataIn(4,0) === "b11001".U) -> "b100110".U(6.W),
(io.dataIn(4,0) === "b11010".U) -> "b010110".U(6.W),
(io.dataIn(4,0) === "b11011".U) -> Mux( ~rd, "b110110".U(6.W), "b001001".U(6.W) ),
(io.dataIn(4,0) === "b11100".U) -> "b001110".U(6.W),
(io.dataIn(4,0) === "b11101".U) -> Mux( ~rd, "b101110".U(6.W), "b010001".U(6.W) ),
(io.dataIn(4,0) === "b11110".U) -> Mux( ~rd, "b011110".U(6.W), "b100001".U(6.W) ),
(io.dataIn(4,0) === "b11111".U) -> Mux( ~rd, "b101011".U(6.W), "b010100".U(6.W) )
))
val b5b6RD = Mux1H(Seq(
(io.dataIn(4,0) === "b00000".U) -> ~rd,
(io.dataIn(4,0) === "b00001".U) -> ~rd,
(io.dataIn(4,0) === "b00010".U) -> ~rd,
(io.dataIn(4,0) === "b00011".U) -> rd,
(io.dataIn(4,0) === "b00100".U) -> ~rd,
(io.dataIn(4,0) === "b00101".U) -> rd,
(io.dataIn(4,0) === "b00110".U) -> rd,
(io.dataIn(4,0) === "b00111".U) -> rd,
(io.dataIn(4,0) === "b01000".U) -> ~rd,
(io.dataIn(4,0) === "b01001".U) -> rd,
(io.dataIn(4,0) === "b01010".U) -> rd,
(io.dataIn(4,0) === "b01011".U) -> rd,
(io.dataIn(4,0) === "b01100".U) -> rd,
(io.dataIn(4,0) === "b01101".U) -> rd,
(io.dataIn(4,0) === "b01110".U) -> rd,
(io.dataIn(4,0) === "b01111".U) -> ~rd,
(io.dataIn(4,0) === "b10000".U) -> ~rd,
(io.dataIn(4,0) === "b10001".U) -> rd,
(io.dataIn(4,0) === "b10010".U) -> rd,
(io.dataIn(4,0) === "b10011".U) -> rd,
(io.dataIn(4,0) === "b10100".U) -> rd,
(io.dataIn(4,0) === "b10101".U) -> rd,
(io.dataIn(4,0) === "b10110".U) -> rd,
(io.dataIn(4,0) === "b10111".U) -> ~rd,
(io.dataIn(4,0) === "b11000".U) -> ~rd,
(io.dataIn(4,0) === "b11001".U) -> rd,
(io.dataIn(4,0) === "b11010".U) -> rd,
(io.dataIn(4,0) === "b11011".U) -> ~rd,
(io.dataIn(4,0) === "b11100".U) -> rd,
(io.dataIn(4,0) === "b11101".U) -> ~rd,
(io.dataIn(4,0) === "b11110".U) -> ~rd,
(io.dataIn(4,0) === "b11111".U) -> ~rd,
))
val b3b4LookUp = Mux1H(Seq(
(io.dataIn(7,5) === "b000".U) -> Mux( ~b5b6RD, "b1011".U(4.W), "b0100".U(4.W) ),
(io.dataIn(7,5) === "b001".U) -> "b1001".U(4.W),
(io.dataIn(7,5) === "b010".U) -> "b0101".U(4.W),
(io.dataIn(7,5) === "b011".U) -> Mux( ~b5b6RD, "b1100".U(4.W), "b0011".U(4.W) ),
(io.dataIn(7,5) === "b100".U) -> Mux( ~b5b6RD, "b1101".U(4.W), "b0010".U(4.W) ),
(io.dataIn(7,5) === "b101".U) -> "b1010".U(4.W),
(io.dataIn(7,5) === "b110".U) -> "b0110".U(4.W),
(io.dataIn(7,5) === "b111".U) -> MuxCase( Mux( ~b5b6RD, "b1110".U(4.W), "b0001".U(4.W) ), Array(
((io.dataIn(4,0) === 17.U || io.dataIn(4,0) === 18.U || io.dataIn(4,0) === 20.U) & ~b5b6RD) -> "b0111".U(4.W), // 17, 18, 20 are special cases
((io.dataIn(4,0) === 11.U || io.dataIn(4,0) === 13.U || io.dataIn(4,0) === 14.U) & b5b6RD) -> "b1000".U(4.W), // 11, 13, 14 are special cases
))
))
val b3b4RD = Mux1H(Seq(
(io.dataIn(7,5) === "b000".U) -> ~b5b6RD,
(io.dataIn(7,5) === "b001".U) -> b5b6RD,
(io.dataIn(7,5) === "b010".U) -> b5b6RD,
(io.dataIn(7,5) === "b011".U) -> b5b6RD,
(io.dataIn(7,5) === "b100".U) -> ~b5b6RD,
(io.dataIn(7,5) === "b101".U) -> b5b6RD,
(io.dataIn(7,5) === "b110".U) -> b5b6RD,
(io.dataIn(7,5) === "b111".U) -> ~b5b6RD,
))
io.dataOut := Cat(b5b6LookUp, b3b4LookUp)
when (io.isEnable) {
rd := b3b4RD
assert( io.dataOut(4,0) =/= 0.U && io.dataOut(4,0) =/= 31.U, "Invalid 8b10b encoding Output!")
assert( io.dataOut(5,1) =/= 0.U && io.dataOut(5,1) =/= 31.U, "Invalid 8b10b encoding Output!")
assert( io.dataOut(6,2) =/= 0.U && io.dataOut(6,2) =/= 31.U, "Invalid 8b10b encoding Output!")
assert( io.dataOut(7,3) =/= 0.U && io.dataOut(7,3) =/= 31.U, "Invalid 8b10b encoding Output!")
assert( io.dataOut(8,4) =/= 0.U && io.dataOut(8,4) =/= 31.U, "Invalid 8b10b encoding Output!")
assert( io.dataOut(9,5) =/= 0.U && io.dataOut(9,5) =/= 31.U, "Invalid 8b10b encoding Output!")
}
}
class b8b10Decode extends Module with RequireAsyncReset{
val io = IO(new Decode_Bundle)
val b5b6LookUp = Mux1H(Seq(
(io.dataIn(9,4) === "b100111".U(6.W) || io.dataIn(9,4) === "b011000".U(6.W) ) -> "b00000".U,
(io.dataIn(9,4) === "b011101".U(6.W) || io.dataIn(9,4) === "b100010".U(6.W) ) -> "b00001".U,
(io.dataIn(9,4) === "b101101".U(6.W) || io.dataIn(9,4) === "b010010".U(6.W) ) -> "b00010".U,
(io.dataIn(9,4) === "b110001".U(6.W)) -> "b00011".U,
(io.dataIn(9,4) === "b110101".U(6.W) || io.dataIn(9,4) === "b001010".U(6.W) ) -> "b00100".U,
(io.dataIn(9,4) === "b101001".U(6.W)) -> "b00101".U,
(io.dataIn(9,4) === "b011001".U(6.W)) -> "b00110".U,
(io.dataIn(9,4) === "b111000".U(6.W) || io.dataIn(9,4) === "b000111".U(6.W) ) -> "b00111".U,
(io.dataIn(9,4) === "b111001".U(6.W) || io.dataIn(9,4) === "b000110".U(6.W) ) -> "b01000".U,
(io.dataIn(9,4) === "b100101".U(6.W)) -> "b01001".U,
(io.dataIn(9,4) === "b010101".U(6.W)) -> "b01010".U,
(io.dataIn(9,4) === "b110100".U(6.W)) -> "b01011".U,
(io.dataIn(9,4) === "b001101".U(6.W)) -> "b01100".U,
(io.dataIn(9,4) === "b101100".U(6.W)) -> "b01101".U,
(io.dataIn(9,4) === "b011100".U(6.W)) -> "b01110".U,
(io.dataIn(9,4) === "b010111".U(6.W) || io.dataIn(9,4) === "b101000".U(6.W) ) -> "b01111".U,
(io.dataIn(9,4) === "b011011".U(6.W) || io.dataIn(9,4) === "b100100".U(6.W) ) -> "b10000".U,
(io.dataIn(9,4) === "b100011".U(6.W)) -> "b10001".U,
(io.dataIn(9,4) === "b010011".U(6.W)) -> "b10010".U,
(io.dataIn(9,4) === "b110010".U(6.W)) -> "b10011".U,
(io.dataIn(9,4) === "b001011".U(6.W)) -> "b10100".U,
(io.dataIn(9,4) === "b101010".U(6.W)) -> "b10101".U,
(io.dataIn(9,4) === "b011010".U(6.W)) -> "b10110".U,
(io.dataIn(9,4) === "b111010".U(6.W) || io.dataIn(9,4) === "b000101".U(6.W) ) -> "b10111".U,
(io.dataIn(9,4) === "b110011".U(6.W) || io.dataIn(9,4) === "b001100".U(6.W) ) -> "b11000".U,
(io.dataIn(9,4) === "b100110".U(6.W)) -> "b11001".U,
(io.dataIn(9,4) === "b010110".U(6.W)) -> "b11010".U,
(io.dataIn(9,4) === "b110110".U(6.W) || io.dataIn(9,4) === "b001001".U(6.W) ) -> "b11011".U,
(io.dataIn(9,4) === "b001110".U(6.W)) -> "b11100".U,
(io.dataIn(9,4) === "b101110".U(6.W) || io.dataIn(9,4) === "b010001".U(6.W) ) -> "b11101".U,
(io.dataIn(9,4) === "b011110".U(6.W) || io.dataIn(9,4) === "b100001".U(6.W) ) -> "b11110".U,
(io.dataIn(9,4) === "b101011".U(6.W) || io.dataIn(9,4) === "b010100".U(6.W) ) -> "b11111".U,
))
val b3b4LookUp = Mux1H(Seq(
(io.dataIn(3,0) === "b1011".U(4.W) || io.dataIn(3,0) === "b0100".U(4.W) ) -> "b000".U,
(io.dataIn(3,0) === "b1001".U(4.W)) -> "b001".U,
(io.dataIn(3,0) === "b0101".U(4.W)) -> "b010".U,
(io.dataIn(3,0) === "b1100".U(4.W) || io.dataIn(3,0) === "b0011".U(4.W) ) -> "b011".U,
(io.dataIn(3,0) === "b1101".U(4.W) || io.dataIn(3,0) === "b0010".U(4.W) ) -> "b100".U,
(io.dataIn(3,0) === "b1010".U(4.W)) -> "b101".U,
(io.dataIn(3,0) === "b0110".U(4.W)) -> "b110".U,
(io.dataIn(3,0) === "b1110".U(4.W) ||
io.dataIn(3,0) === "b0001".U(4.W) ||
io.dataIn(3,0) === "b0111".U(4.W) ||
io.dataIn(3,0) === "b1000".U(4.W)) -> "b111".U,
))
io.dataOut := Cat(b3b4LookUp, b5b6LookUp)
}

336
src/main/scala/backBoard/shin/Interface.scala
View File

@@ -52,6 +52,10 @@ class CommonRegisterBundle extends Bundle{
val refTop = UInt(3.W)
val bias = UInt(2.W)
val dwupEx = UInt(16.W)
val b8b4Sel = UInt(16.W)
val cdrParam = UInt(16.W)
val softResetCode = Vec(4, UInt(8.W))
@@ -95,10 +99,6 @@ class CommonRegisterBundle extends Bundle{
val syncPeroid = UInt(32.W)
val recoTimeStamp = UInt(64.W) //时钟补偿寄存器
val localPeroid = UInt(32.W)
val localPoint = UInt(64.W)
val custom = Vec( 128, UInt(8.W) )
val smUsedDepth = Vec(8, UInt(8.W))
@@ -122,6 +122,7 @@ class MasterRegisterBundle extends Bundle{
val isRecCRCErr = UInt(4.W)
val rplTimeStampTx = UInt(16.W)
val timeStampOffset = UInt(64.W)
}
@@ -140,7 +141,8 @@ class SlaveRegisterBundle extends Bundle{
val slvDeltaTime = UInt(32.W) //从站时间戳差值
val deltaFinal = UInt(64.W) //当前时间戳与主站时间差
val lvdsWriteAble = UInt(16.W)
def isLVDSWriteAble = lvdsWriteAble(15,8) === "h58".U & lvdsWriteAble.extract(0)
}
@@ -210,6 +212,7 @@ class InterfaceIO extends Bundle{
val hwSerial = Input(UInt(48.W))
val uniCode = Input(UInt(64.W))
val isPllCfg = Output(Bool())
}
@@ -263,6 +266,7 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
Seq(
(addr === "h18".U ) -> sReg.lvdsWriteAble.extract(0),
(addr === "h20".U & isMstMode) -> Cat(mReg.rxSM, mReg.txSM, 0.U(1.W) ),
(addr === "h22".U & isMstMode) -> mReg.isRecCRCErr,
//(addr === "h21".U & isMstMode) -> mReg.txLength,
@@ -294,7 +298,20 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
(addr === ("h48".U(16.W) + i.U) ) -> cReg.xtal( 8*i+7,8*i+0 )
}) ++
((0 until 2).map{ i =>
(addr === ("h4c".U(16.W) + i.U) ) -> cReg.b8b4Sel( 8*i+7,8*i+0 )
}) ++
((0 until 2).map{ i =>
(addr === ("h4e".U(16.W) + i.U) ) -> cReg.cdrParam( 8*i+7,8*i+0 )
}) ++
Seq(
(addr === "h4a".U ) -> cReg.dwupEx.extract(0),
(addr === "h4c".U ) -> cReg.b8b4Sel.extract(0),
(addr === "h4e".U ) -> cReg.cdrParam(7,0),
(addr === "h50".U ) -> cReg.anamuxSel,
(addr === "h51".U ) -> cReg.ldo2p5,
(addr === "h52".U ) -> cReg.ldo1p1,
@@ -379,13 +396,13 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
Seq(
//本地时钟
(addr === "h100".U ) -> cReg.timeStamp(7,0),
(addr === "h101".U ) -> RegEnable(cReg.timeStamp(15,8), isEnR & (addrr === "h100".U)),
(addr === "h102".U ) -> RegEnable(cReg.timeStamp(23,16), isEnR & (addrr === "h100".U)),
(addr === "h103".U ) -> RegEnable(cReg.timeStamp(31,24), isEnR & (addrr === "h100".U)),
(addr === "h104".U ) -> RegEnable(cReg.timeStamp(39,32), isEnR & (addrr === "h100".U)),
(addr === "h105".U ) -> RegEnable(cReg.timeStamp(47,40), isEnR & (addrr === "h100".U)),
(addr === "h106".U ) -> RegEnable(cReg.timeStamp(55,48), isEnR & (addrr === "h100".U)),
(addr === "h107".U ) -> RegEnable(cReg.timeStamp(63,56), isEnR & (addrr === "h100".U)),
(addr === "h101".U ) -> RegEnable(cReg.timeStamp(15,8), 0.U(8.W), isEnR & (addrr === "h100".U)),
(addr === "h102".U ) -> RegEnable(cReg.timeStamp(23,16), 0.U(8.W), isEnR & (addrr === "h100".U)),
(addr === "h103".U ) -> RegEnable(cReg.timeStamp(31,24), 0.U(8.W), isEnR & (addrr === "h100".U)),
(addr === "h104".U ) -> RegEnable(cReg.timeStamp(39,32), 0.U(8.W), isEnR & (addrr === "h100".U)),
(addr === "h105".U ) -> RegEnable(cReg.timeStamp(47,40), 0.U(8.W), isEnR & (addrr === "h100".U)),
(addr === "h106".U ) -> RegEnable(cReg.timeStamp(55,48), 0.U(8.W), isEnR & (addrr === "h100".U)),
(addr === "h107".U ) -> RegEnable(cReg.timeStamp(63,56), 0.U(8.W), isEnR & (addrr === "h100".U)),
//参考主站时钟
(addr === "h108".U & isSlvMode) -> sReg.deltaFinal(7,0),
@@ -411,13 +428,13 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
//校准后的时钟
(addr === "h118".U ) -> cReg.recoTimeStamp(7,0),
(addr === "h119".U ) -> RegEnable(cReg.recoTimeStamp(15,8), isEnR & (addrr === "h118".U)),
(addr === "h11a".U ) -> RegEnable(cReg.recoTimeStamp(23,16), isEnR & (addrr === "h118".U)),
(addr === "h11b".U ) -> RegEnable(cReg.recoTimeStamp(31,24), isEnR & (addrr === "h118".U)),
(addr === "h11c".U ) -> RegEnable(cReg.recoTimeStamp(39,32), isEnR & (addrr === "h118".U)),
(addr === "h11d".U ) -> RegEnable(cReg.recoTimeStamp(47,40), isEnR & (addrr === "h118".U)),
(addr === "h11e".U ) -> RegEnable(cReg.recoTimeStamp(55,48), isEnR & (addrr === "h118".U)),
(addr === "h11f".U ) -> RegEnable(cReg.recoTimeStamp(63,56), isEnR & (addrr === "h118".U)),
(addr === "h119".U ) -> RegEnable(cReg.recoTimeStamp(15,8), 0.U(8.W), isEnR & (addrr === "h118".U)),
(addr === "h11a".U ) -> RegEnable(cReg.recoTimeStamp(23,16), 0.U(8.W), isEnR & (addrr === "h118".U)),
(addr === "h11b".U ) -> RegEnable(cReg.recoTimeStamp(31,24), 0.U(8.W), isEnR & (addrr === "h118".U)),
(addr === "h11c".U ) -> RegEnable(cReg.recoTimeStamp(39,32), 0.U(8.W), isEnR & (addrr === "h118".U)),
(addr === "h11d".U ) -> RegEnable(cReg.recoTimeStamp(47,40), 0.U(8.W), isEnR & (addrr === "h118".U)),
(addr === "h11e".U ) -> RegEnable(cReg.recoTimeStamp(55,48), 0.U(8.W), isEnR & (addrr === "h118".U)),
(addr === "h11f".U ) -> RegEnable(cReg.recoTimeStamp(63,56), 0.U(8.W), isEnR & (addrr === "h118".U)),
(addr === "h120".U ) -> cReg.syncCfg,
@@ -462,19 +479,14 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
(addr === "h146".U ) -> cReg.syncOffset(3)(23,16),
(addr === "h147".U ) -> cReg.syncOffset(3)(31,24),
(addr === "h148".U ) -> cReg.localPoint(7,0),
(addr === "h149".U ) -> cReg.localPoint(15,8),
(addr === "h14a".U ) -> cReg.localPoint(23,16),
(addr === "h14b".U ) -> cReg.localPoint(31,24),
(addr === "h14c".U ) -> cReg.localPoint(39,32),
(addr === "h14d".U ) -> cReg.localPoint(47,40),
(addr === "h14e".U ) -> cReg.localPoint(55,48),
(addr === "h14f".U ) -> cReg.localPoint(63,56),
(addr === "h150".U ) -> cReg.localPeroid(7,0),
(addr === "h151".U ) -> cReg.localPeroid(15,8),
(addr === "h152".U ) -> cReg.localPeroid(23,16),
(addr === "h153".U ) -> cReg.localPeroid(31,24),
(addr === "h148".U ) -> mReg.timeStampOffset(7,0),
(addr === "h149".U ) -> mReg.timeStampOffset(15,8),
(addr === "h14a".U ) -> mReg.timeStampOffset(23,16),
(addr === "h14b".U ) -> mReg.timeStampOffset(31,24),
(addr === "h14c".U ) -> mReg.timeStampOffset(39,32),
(addr === "h14d".U ) -> mReg.timeStampOffset(47,40),
(addr === "h14e".U ) -> mReg.timeStampOffset(55,48),
(addr === "h14f".U ) -> mReg.timeStampOffset(63,56),
) ++
( 0 until 128 ).map{ i =>
@@ -603,7 +615,7 @@ trait InterfaceMCUop{ this: InterfaceBase =>
))
datar := MuxCase( 0.U, Array(
((addrr & "hF800".U) === "h0000".U) -> RegEnable( AcquireReg(addr = addrr), isEnR ),
((addrr & "hF800".U) === "h0000".U) -> RegEnable( AcquireReg(addr = addrr), 0.U(8.W), isEnR ),
((addrr & "hF800".U) === "h0800".U) -> io.sram_r(0).datar,
((addrr & "hF800".U) === "h1000".U) -> 0.U,
((addrr & "hF800".U) === "h1800".U) -> io.sram_r(1).datar,
@@ -735,34 +747,35 @@ trait InterfaceCheckSM{ this: InterfaceBase =>
io.uSMenq(3) := isEnW & (( addrw & "hF800".U ) === "h4000".U) & (addrw(10,0) === cReg.smTrigLen(7) - 1.U)
}
trait InterfaceLVDSop{ this: InterfaceBase =>
trait InterfaceEBMMU{ this: InterfaceBase =>
io.lvds.datar := RegEnable(AcquireReg(addr = io.lvds.addrr), io.lvds.isEnR)
io.lvds.datar := RegEnable(AcquireReg(addr = io.lvds.addrr), 0.U(8.W), io.lvds.isEnR)
( 0 until 16 ).map{ i =>
sReg.ebmmu(i).lAddr := Cat(
RegEnable( io.lvds.dataw(5,0), 0.U(8.W), io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h203".U(16.W) + (10*i).U )) ),
RegEnable( io.lvds.dataw, 0.U(8.W), io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h202".U(16.W) + (10*i).U )) ),
RegEnable( io.lvds.dataw, 0.U(8.W), io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h201".U(16.W) + (10*i).U )) ),
RegEnable( io.lvds.dataw, 0.U(8.W), io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h200".U(16.W) + (10*i).U )) ),
RegEnable( io.lvds.dataw(5,0), 0.U(8.W), sReg.isLVDSWriteAble & io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h203".U(16.W) + (10*i).U )) ),
RegEnable( io.lvds.dataw, 0.U(8.W), sReg.isLVDSWriteAble & io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h202".U(16.W) + (10*i).U )) ),
RegEnable( io.lvds.dataw, 0.U(8.W), sReg.isLVDSWriteAble & io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h201".U(16.W) + (10*i).U )) ),
RegEnable( io.lvds.dataw, 0.U(8.W), sReg.isLVDSWriteAble & io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h200".U(16.W) + (10*i).U )) ),
)
sReg.ebmmu(i).pAddr := Cat(
RegEnable( io.lvds.dataw, 0.U(8.W), io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h205".U(16.W) + (10*i).U )) ),
RegEnable( io.lvds.dataw, 0.U(8.W), io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h204".U(16.W) + (10*i).U )) ),
RegEnable( io.lvds.dataw, 0.U(8.W), sReg.isLVDSWriteAble & io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h205".U(16.W) + (10*i).U )) ),
RegEnable( io.lvds.dataw, 0.U(8.W), sReg.isLVDSWriteAble & io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h204".U(16.W) + (10*i).U )) ),
)
sReg.ebmmu(i).length := Cat(
RegEnable( io.lvds.dataw, 0.U(8.W), io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h207".U(16.W) + (10*i).U )) ),
RegEnable( io.lvds.dataw, 0.U(8.W), io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h206".U(16.W) + (10*i).U )) ),
RegEnable( io.lvds.dataw, 0.U(8.W), sReg.isLVDSWriteAble & io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h207".U(16.W) + (10*i).U )) ),
RegEnable( io.lvds.dataw, 0.U(8.W), sReg.isLVDSWriteAble & io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h206".U(16.W) + (10*i).U )) ),
)
sReg.ebmmu(i).op :=
RegEnable( io.lvds.dataw, 0.U(8.W), io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h208".U(16.W) + (10*i).U )) )
RegEnable( io.lvds.dataw, 0.U(8.W), sReg.isLVDSWriteAble & io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h208".U(16.W) + (10*i).U )) )
sReg.ebmmu(i).isEnable :=
RegEnable( io.lvds.dataw.extract(0), false.B, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h209".U(16.W) + (10*i).U )) )
RegEnable( io.lvds.dataw.extract(0), false.B, sReg.isLVDSWriteAble & io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h209".U(16.W) + (10*i).U )) )
}
}
@@ -776,10 +789,11 @@ trait InterfaceSync{ this: InterfaceBase =>
cReg.syncWidth(i) := syncWidth(i)
}
val syncPoint = RegInit(0.U(64.W)); cReg.syncPoint := syncPoint
val timeStampOffset = RegInit(0.U(64.W)); mReg.timeStampOffset := timeStampOffset
val timeStampOffset_WRCopy = RegInit(0.U(64.W))
val syncPoint = RegInit("hFFFFFFFFFFFFFFFF".U(64.W)); cReg.syncPoint := syncPoint
val syncPoint_WRCopy = RegInit("hFFFFFFFFFFFFFFFF".U(64.W))
val syncPeroid = RegInit(0.U(32.W)); cReg.syncPeroid := syncPeroid
val localPoint = RegInit(0.U(64.W)); cReg.localPoint := localPoint
val localPeroid = RegInit(0.U(32.W)); cReg.localPeroid := localPeroid
val syncOffset = for( i <- 0 until 4 ) yield { RegInit(0.U(32.W)) } //空开0
for( i <- 0 until 4 ) {
@@ -792,29 +806,30 @@ trait InterfaceSync{ this: InterfaceBase =>
}
for( i <- 0 until 4 ){
when( io.lvds.addrw === ("h122".U(16.W) + (2*i).U)){
syncWidth(i) := Cat( syncWidth(i)(15,8), io.lvds.dataw )
} .elsewhen( io.lvds.addrw === ("h123".U(16.W) + (2*i).U) ){
syncWidth(i) := Cat( io.lvds.dataw, syncWidth(i)(7,0) )
when( addrw === ("h122".U(16.W) + (2*i).U)){
syncWidth(i) := Cat( syncWidth(i)(15,8), dataw )
} .elsewhen( addrw === ("h123".U(16.W) + (2*i).U) ){
syncWidth(i) := Cat( dataw, syncWidth(i)(7,0) )
}
}
when( addrw === "h130".U ){
syncPoint := Cat( syncPoint(63,8), dataw )
syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,8), dataw )
} .elsewhen( addrw === "h131".U ){
syncPoint := Cat( syncPoint(63,16), dataw, syncPoint(7,0) )
syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,16), dataw, syncPoint_WRCopy(7,0) )
} .elsewhen( addrw === "h132".U ){
syncPoint := Cat( syncPoint(63,24), dataw, syncPoint(15,0) )
syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,24), dataw, syncPoint_WRCopy(15,0) )
} .elsewhen( addrw === "h133".U ){
syncPoint := Cat( syncPoint(63,32), dataw, syncPoint(23,0) )
syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,32), dataw, syncPoint_WRCopy(23,0) )
} .elsewhen( addrw === "h134".U ){
syncPoint := Cat( syncPoint(63,40), dataw, syncPoint(31,0) )
syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,40), dataw, syncPoint_WRCopy(31,0) )
} .elsewhen( addrw === "h135".U ){
syncPoint := Cat( syncPoint(63,48), dataw, syncPoint(39,0) )
syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,48), dataw, syncPoint_WRCopy(39,0) )
} .elsewhen( addrw === "h136".U ){
syncPoint := Cat( syncPoint(63,56), dataw, syncPoint(47,0) )
syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,56), dataw, syncPoint_WRCopy(47,0) )
} .elsewhen( addrw === "h137".U ){
syncPoint := Cat( dataw, syncPoint(55,0) )
syncPoint_WRCopy := Cat( dataw, syncPoint_WRCopy(55,0) )
syncPoint := Cat( dataw, syncPoint_WRCopy(55,0) )
}
.elsewhen( addrw === "h138".U ){
@@ -828,34 +843,24 @@ trait InterfaceSync{ this: InterfaceBase =>
}
.elsewhen( addrw === "h148".U ){
localPoint := Cat( localPoint(63,8), dataw )
timeStampOffset_WRCopy := Cat( timeStampOffset_WRCopy(63,8), dataw )
} .elsewhen( addrw === "h149".U ){
localPoint := Cat( localPoint(63,16), dataw, localPoint(7,0) )
timeStampOffset_WRCopy := Cat( timeStampOffset_WRCopy(63,16), dataw, timeStampOffset_WRCopy(7,0) )
} .elsewhen( addrw === "h14a".U ){
localPoint := Cat( localPoint(63,24), dataw, localPoint(15,0) )
timeStampOffset_WRCopy := Cat( timeStampOffset_WRCopy(63,24), dataw, timeStampOffset_WRCopy(15,0) )
} .elsewhen( addrw === "h14b".U ){
localPoint := Cat( localPoint(63,32), dataw, localPoint(23,0) )
timeStampOffset_WRCopy := Cat( timeStampOffset_WRCopy(63,32), dataw, timeStampOffset_WRCopy(23,0) )
} .elsewhen( addrw === "h14c".U ){
localPoint := Cat( localPoint(63,40), dataw, localPoint(31,0) )
timeStampOffset_WRCopy := Cat( timeStampOffset_WRCopy(63,40), dataw, timeStampOffset_WRCopy(31,0) )
} .elsewhen( addrw === "h14d".U ){
localPoint := Cat( localPoint(63,48), dataw, localPoint(39,0) )
timeStampOffset_WRCopy := Cat( timeStampOffset_WRCopy(63,48), dataw, timeStampOffset_WRCopy(39,0) )
} .elsewhen( addrw === "h14e".U ){
localPoint := Cat( localPoint(63,56), dataw, localPoint(47,0) )
timeStampOffset_WRCopy := Cat( timeStampOffset_WRCopy(63,56), dataw, timeStampOffset_WRCopy(47,0) )
} .elsewhen( addrw === "h14f".U ){
localPoint := Cat( dataw, localPoint(55,0) )
timeStampOffset_WRCopy := Cat( dataw, timeStampOffset_WRCopy(55,0) )
timeStampOffset := Cat( dataw, timeStampOffset_WRCopy(55,0) )
}
.elsewhen( addrw === "h150".U ){
localPeroid := Cat( localPeroid(31,8), dataw )
} .elsewhen( addrw === "h151".U ){
localPeroid := Cat( localPeroid(31,16), dataw, localPeroid(7,0) )
} .elsewhen( addrw === "h152".U ){
localPeroid := Cat( localPeroid(31,24), dataw, localPeroid(15,0) )
} .elsewhen( addrw === "h153".U ){
localPeroid := Cat( dataw, localPeroid(23,0) )
}
for( i <- 1 until 4 ){
when( addrw === ("h13c".U(16.W) + (4*(i-1)).U) ){
@@ -871,7 +876,6 @@ trait InterfaceSync{ this: InterfaceBase =>
}
when( io.lvds.isEnW ){
when( io.lvds.addrw === "h120".U ){
@@ -887,21 +891,22 @@ trait InterfaceSync{ this: InterfaceBase =>
}
.elsewhen( io.lvds.addrw === "h130".U ){
syncPoint := Cat( syncPoint(63,8), io.lvds.dataw )
syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,8), io.lvds.dataw )
} .elsewhen( io.lvds.addrw === "h131".U ){
syncPoint := Cat( syncPoint(63,16), io.lvds.dataw, syncPoint(7,0) )
syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,16), io.lvds.dataw, syncPoint_WRCopy(7,0) )
} .elsewhen( io.lvds.addrw === "h132".U ){
syncPoint := Cat( syncPoint(63,24), io.lvds.dataw, syncPoint(15,0) )
syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,24), io.lvds.dataw, syncPoint_WRCopy(15,0) )
} .elsewhen( io.lvds.addrw === "h133".U ){
syncPoint := Cat( syncPoint(63,32), io.lvds.dataw, syncPoint(23,0) )
syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,32), io.lvds.dataw, syncPoint_WRCopy(23,0) )
} .elsewhen( io.lvds.addrw === "h134".U ){
syncPoint := Cat( syncPoint(63,40), io.lvds.dataw, syncPoint(31,0) )
syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,40), io.lvds.dataw, syncPoint_WRCopy(31,0) )
} .elsewhen( io.lvds.addrw === "h135".U ){
syncPoint := Cat( syncPoint(63,48), io.lvds.dataw, syncPoint(39,0) )
syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,48), io.lvds.dataw, syncPoint_WRCopy(39,0) )
} .elsewhen( io.lvds.addrw === "h136".U ){
syncPoint := Cat( syncPoint(63,56), io.lvds.dataw, syncPoint(47,0) )
syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,56), io.lvds.dataw, syncPoint_WRCopy(47,0) )
} .elsewhen( io.lvds.addrw === "h137".U ){
syncPoint := Cat( io.lvds.dataw, syncPoint(55,0) )
syncPoint_WRCopy := Cat( io.lvds.dataw, syncPoint_WRCopy(55,0) )
syncPoint := Cat( io.lvds.dataw, syncPoint_WRCopy(55,0) )
}
.elsewhen( io.lvds.addrw === "h138".U ){
@@ -914,35 +919,6 @@ trait InterfaceSync{ this: InterfaceBase =>
syncPeroid := Cat( io.lvds.dataw, syncPeroid(23,0) )
}
.elsewhen( io.lvds.addrw === "h148".U ){
localPoint := Cat( localPoint(63,8), io.lvds.dataw )
} .elsewhen( io.lvds.addrw === "h149".U ){
localPoint := Cat( localPoint(63,16), io.lvds.dataw, localPoint(7,0) )
} .elsewhen( io.lvds.addrw === "h14a".U ){
localPoint := Cat( localPoint(63,24), io.lvds.dataw, localPoint(15,0) )
} .elsewhen( io.lvds.addrw === "h14b".U ){
localPoint := Cat( localPoint(63,32), io.lvds.dataw, localPoint(23,0) )
} .elsewhen( io.lvds.addrw === "h14c".U ){
localPoint := Cat( localPoint(63,40), io.lvds.dataw, localPoint(31,0) )
} .elsewhen( io.lvds.addrw === "h14d".U ){
localPoint := Cat( localPoint(63,48), io.lvds.dataw, localPoint(39,0) )
} .elsewhen( io.lvds.addrw === "h14e".U ){
localPoint := Cat( localPoint(63,56), io.lvds.dataw, localPoint(47,0) )
} .elsewhen( io.lvds.addrw === "h14f".U ){
localPoint := Cat( io.lvds.dataw, localPoint(55,0) )
}
.elsewhen( io.lvds.addrw === "h150".U ){
localPeroid := Cat( localPeroid(31,8), io.lvds.dataw )
} .elsewhen( io.lvds.addrw === "h151".U ){
localPeroid := Cat( localPeroid(31,16), io.lvds.dataw, localPeroid(7,0) )
} .elsewhen( io.lvds.addrw === "h152".U ){
localPeroid := Cat( localPeroid(31,24), io.lvds.dataw, localPeroid(15,0) )
} .elsewhen( io.lvds.addrw === "h153".U ){
localPeroid := Cat( io.lvds.dataw, localPeroid(23,0) )
}
for( i <- 1 until 4 ){
when( io.lvds.addrw === ("h13c".U(16.W) + (4*(i-1)).U) ){
syncOffset(i) := Cat( syncOffset(i)(31,8), io.lvds.dataw )
@@ -956,14 +932,14 @@ trait InterfaceSync{ this: InterfaceBase =>
}
}
cReg.timeStamp := RegNext( cReg.timeStamp + 1.U, 0.U )
cReg.timeStamp := RegNext( cReg.timeStamp + 1.U, 1.U(64.W) )
cReg.mstDeltaTime := io.mstDeltaTime
sReg.deltaFinal := io.deltaFinal
cReg.recoTimeStamp :=
Mux(isMstMode, cReg.timeStamp,
RegNext( cReg.timeStamp + sReg.deltaFinal )
Mux(isMstMode, cReg.timeStamp + mReg.timeStampOffset,
RegNext( cReg.timeStamp + sReg.deltaFinal, 0.U(64.W) )
)
sReg.slvDeltaTime := io.slvDeltaTime
@@ -971,19 +947,40 @@ trait InterfaceSync{ this: InterfaceBase =>
val syncOffsetCnt = for( i <- 0 until 4 ) yield { RegInit("hFFFFFFFF".U(32.W)) } //空开第0位
val syncResetCnt = for( i <- 0 until 4 ) yield { RegInit(0.U(16.W)) } //空开第0位
val recoTimeStamp_Copy = RegInit(1.U(64.W))
when( cReg.syncPoint === cReg.recoTimeStamp ){ //时间到达sync0时间点
when(
cReg.syncPoint === recoTimeStamp_Copy ||
(io.lvds.addrw === "h120".U & io.lvds.isEnW) || //写syncCfg
(io.lvds.addrw === "h137".U & io.lvds.isEnW) || //写syncPoint
(io.lvds.addrw === "h13B".U & io.lvds.isEnW) || //写syncPeroid
(addrw === "h120".U & isEnW) || //写syncCfg
(addrw === "h137".U & isEnW) || //写syncPoint
(addrw === "h13B".U & isEnW) //写syncPeroid
){
recoTimeStamp_Copy := cReg.timeStamp + sReg.deltaFinal
} .otherwise{
recoTimeStamp_Copy := recoTimeStamp_Copy + 1.U
}
when( cReg.syncPoint === recoTimeStamp_Copy ){ //时间到达sync0时间点
syncSign(0) := true.B
syncPoint := syncPoint + cReg.syncPeroid
} .elsewhen( ~cReg.syncCfg(4+0) & syncResetCnt(0) === cReg.syncWidth(0) ){
syncSign(0) := false.B
} .elsewhen( cReg.syncCfg(4+0) & isEnW & addrw === "h122".U ){
syncSign(0) := false.B
}
when( cReg.syncPoint <= recoTimeStamp_Copy ){
syncPoint := syncPoint + cReg.syncPeroid
}
for( i <- 1 until 4 ) {
when( cReg.syncPoint === cReg.recoTimeStamp ){ //时间到达sync0时间点
when( cReg.syncPoint === recoTimeStamp_Copy ){ //时间到达sync0时间点
syncOffsetCnt(i) := 0.U
} .elsewhen( syncOffsetCnt(i) < cReg.syncOffset(i) ){
syncOffsetCnt(i) := syncOffsetCnt(i) + 1.U
@@ -1017,13 +1014,6 @@ trait InterfaceSync{ this: InterfaceBase =>
io.sync(3) := cReg.syncCfg.extract(3) & syncSign(3)
val isLocalSyncInt = cReg.localPoint === cReg.recoTimeStamp
when( isLocalSyncInt ){ //时间到达localSync时间点
localPoint := cReg.localPoint + cReg.localPeroid
}
}
trait InterfaceWdt{ this: InterfaceBase =>
@@ -1081,6 +1071,38 @@ trait InterfaceSystem{ this: InterfaceBase =>
cReg.softResetCode(3) := RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h43".U )
cReg.dwupEx :=
Cat(
RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h4b".U ),
RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h4a".U )
)
cReg.b8b4Sel :=
Cat(
RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h4d".U ),
RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h4c".U )
)
cReg.cdrParam :=
Cat(
RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h4f".U ),
RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h4e".U )
)
val lvdsWriteAble = RegInit(0.U(16.W)); sReg.lvdsWriteAble := lvdsWriteAble
when( io.lvds.isEnW & (io.lvds.addrw === "h19".U(16.W)) ){
lvdsWriteAble := Cat( io.lvds.dataw, lvdsWriteAble(7,0) )
} .elsewhen( isEnW & (addrw === "h19".U(16.W)) ){
lvdsWriteAble := Cat( dataw, lvdsWriteAble(7,0) )
} .elsewhen( io.lvds.isEnW & (io.lvds.addrw === "h18".U(16.W)) ){
lvdsWriteAble := Cat( lvdsWriteAble(15,8), io.lvds.dataw )
} .elsewhen( isEnW & (addrw === "h18".U(16.W)) ){
lvdsWriteAble := Cat( lvdsWriteAble(15,8), dataw )
}
}
trait InterfaceInterrupt{ this: InterfaceBase =>
cReg.intEnable :=
Cat(
1.U(1.W), //复位中断，时钟为1 //31 上电复位
@@ -1118,16 +1140,11 @@ trait InterfaceSystem{ this: InterfaceBase =>
intStatus(1) := true.B
}
//主站发送周期到了
val isLocalSyncInt: Bool
when( isLocalSyncInt ){
intStatus(2) := true.B
}
//外部latch中断
val isLatchEvent =
(RegNext( cReg.event.latchStatus(0) ) =/= cReg.event.latchStatus(0)) |
(RegNext( cReg.event.latchStatus(1) ) =/= cReg.event.latchStatus(1))
(RegNext( cReg.event.latchStatus(0), false.B ) =/= cReg.event.latchStatus(0)) |
(RegNext( cReg.event.latchStatus(1), false.B ) =/= cReg.event.latchStatus(1))
when(isLatchEvent){
intStatus(3) := true.B
@@ -1164,12 +1181,17 @@ trait InterfaceSystem{ this: InterfaceBase =>
intStatus(19) := true.B
}
val intHWErr = Seq(
( ~RegNext(io.intHWTrig(0), false.B) & io.intHWTrig(0)),
( ~RegNext(io.intHWTrig(1), false.B) & io.intHWTrig(1))
)
//下行接收硬件错误
when( io.intHWTrig(0) ){
when( intHWErr(0) ){
intStatus(29) := true.B
}
//上行接收硬件错误
when( io.intHWTrig(1) ){
when( intHWErr(1) ){
intStatus(30) := true.B
}
@@ -1199,33 +1221,29 @@ trait InterfaceSystem{ this: InterfaceBase =>
val trigIntPulse =
(io.intMstTrig(0) & cReg.intEnable(0)) | //主站发送完成
(io.intMstTrig(1) & cReg.intEnable(1)) | //主站接收完成
(isLocalSyncInt & cReg.intEnable(2)) | //主站发送周期到了
(isLatchEvent & cReg.intEnable(3)) | //latch Event
(isWdtTrigAndEnable & cReg.intEnable(4)) | //主站接收看门狗溢出
(0 until 8).map{ i => io.intSlvTrig(i) & cReg.intEnable(8+i)}.reduce(_|_) | //从站SM请求
(0 until 4).map{ i => io.intTransEnd(i) & cReg.intEnable(16+i)}.reduce(_|_) | //传输完成请求 16,17,18,19
isMstRecCRCErr | //override //主站状态下19为上行crc接收错误 //不会同时发生
io.intHWTrig(0) | //下行接收硬件错误
io.intHWTrig(1) //上行接收硬件错误
intHWErr(0) | //下行接收硬件错误
intHWErr(1) //上行接收硬件错误
when( intPulseResetCnt === intPulseWidth ){
intPulse := false.B
} .elsewhen( trigIntPulse ){
when( trigIntPulse ){
intPulse := true.B
}
} .elsewhen( intPulseResetCnt === intPulseWidth ){
intPulse := false.B
}
when( trigIntPulse ){
intPulseResetCnt := 0.U
} .elsewhen( (intPulseResetCnt < intPulseWidth) & (intPulse === true.B) ){
} .elsewhen( (intPulseResetCnt <= intPulseWidth) & (intPulse === true.B) ){
intPulseResetCnt := intPulseResetCnt + 1.U
}
io.interrupt := Mux( isLevelInt, (cReg.intStatus & cReg.intEnable).orR, intPulse)
}
trait InterfaceEvent{ this: InterfaceBase =>
val isPosedgeOnce = for( i <- 0 until 2 ) yield RegEnable( dataw.extract(2), false.B, isEnW & ( addrw === ( "h500".U + (i*2).U ) ))
val isNegedgeOnce = for( i <- 0 until 2 ) yield RegEnable( dataw.extract(3), false.B, isEnW & ( addrw === ( "h500".U + (i*2).U ) ))
@@ -1312,11 +1330,13 @@ trait InterfaceAnalog{ this: InterfaceBase =>
)
cReg.anamuxSel := RegEnable( dataw, "h0".U(8.W), isEnW & addrw === "h50".U )
cReg.ldo2p5 := RegEnable( dataw, "h87".U(8.W), isEnW & addrw === "h51".U )
cReg.ldo1p1 := RegEnable( dataw, "h87".U(8.W), isEnW & addrw === "h52".U )
cReg.refTop := RegEnable( dataw, "h0".U(8.W), isEnW & addrw === "h53".U )
cReg.bias := RegEnable( dataw, "h0".U(8.W), isEnW & addrw === "h54".U )
cReg.anamuxSel := RegEnable( dataw, "h0".U(8.W), isEnW & addrw === "h50".U )
cReg.ldo2p5 := RegEnable( dataw, "h87".U(8.W), isEnW & addrw === "h51".U )
cReg.ldo1p1 := RegEnable( dataw, "h87".U(8.W), isEnW & addrw === "h52".U )
cReg.refTop := RegEnable( dataw, "h0".U(8.W), isEnW & addrw === "h53".U )
cReg.bias := RegEnable( dataw, "h0".U(8.W), isEnW & addrw === "h54".U )
io.isPllCfg := isEnW & addrw === "h45".U
}
trait InterfaceStat{ this: InterfaceBase =>
@@ -1450,11 +1470,12 @@ trait InterfaceStat{ this: InterfaceBase =>
class Interface extends InterfaceBase
with InterfaceMCUop
with InterfaceCheckSM
with InterfaceLVDSop
with InterfaceEBMMU
with InterfaceSync
with InterfaceStat
with InterfaceWdt
with InterfaceSystem
with InterfaceInterrupt
with InterfaceEvent
with InterfaceAnalog
{
@@ -1473,9 +1494,6 @@ with InterfaceAnalog
sReg.localDevIndex := io.localDevIndex
// sReg.isDevOnLeft := io.isDevOnLeft
// sReg.isDevOnLeftModify := io.isDevOnLeftModify
// sReg.indexOfLeftDev := io.indexOfLeftDev
sReg.isDevOnRight := io.isDevOnRight
sReg.isDevOnRightModify := io.isDevOnRightModify
sReg.indexOfRightDev := io.indexOfRightDev

37
src/main/scala/backBoard/shin/MasterParser.scala
View File

@@ -30,13 +30,12 @@ class MasterParserIO extends Bundle{
abstract class MasterParserBase extends Module with RequireAsyncReset{
val io: MasterParserIO = IO(new MasterParserIO)
val txCnt = Reg(UInt(12.W))
val txLen = Reg(UInt(11.W))
val txAddr = Reg(UInt(15.W))
val rxCnt = Reg(UInt(12.W))
val rxLen = Reg(UInt(11.W))
val rxAddr = Reg(UInt(15.W))
val txCnt = RegInit(0.U(12.W))
val txLen = RegInit(0.U(11.W))
val txAddr = RegInit(0.U(15.W))
val rxCnt = RegInit(0.U(12.W))
val rxLen = RegInit(0.U(11.W))
val rxAddr = RegInit(0.U(15.W))
val reqReady = RegInit(true.B)
@@ -114,14 +113,14 @@ abstract class MasterParserBase extends Module with RequireAsyncReset{
io.downOut.bits.tdata := Mux1H(Seq(
( txCnt < txLen ) ->
MuxCase( io.sram_r.datar, Array(
( isRplTimeStamp & ( txCnt === rplCnt0 ) ) -> io.cReg.timeStamp(7,0),
( isRplTimeStamp & ( txCnt === rplCnt1 ) ) -> RegEnable(io.cReg.timeStamp(15,8), io.downOut.fire & txCnt === rplCnt0 ),
( isRplTimeStamp & ( txCnt === rplCnt2 ) ) -> RegEnable(io.cReg.timeStamp(23,16), io.downOut.fire & txCnt === rplCnt0 ),
( isRplTimeStamp & ( txCnt === rplCnt3 ) ) -> RegEnable(io.cReg.timeStamp(31,24), io.downOut.fire & txCnt === rplCnt0 ),
( isRplTimeStamp & ( txCnt === rplCnt4 ) ) -> RegEnable(io.cReg.timeStamp(39,32), io.downOut.fire & txCnt === rplCnt0 ),
( isRplTimeStamp & ( txCnt === rplCnt5 ) ) -> RegEnable(io.cReg.timeStamp(47,40), io.downOut.fire & txCnt === rplCnt0 ),
( isRplTimeStamp & ( txCnt === rplCnt6 ) ) -> RegEnable(io.cReg.timeStamp(55,48), io.downOut.fire & txCnt === rplCnt0 ),
( isRplTimeStamp & ( txCnt === rplCnt7 ) ) -> RegEnable(io.cReg.timeStamp(63,56), io.downOut.fire & txCnt === rplCnt0 ),
( isRplTimeStamp & ( txCnt === rplCnt0 ) ) -> RegEnable(io.cReg.recoTimeStamp(7,0), 0.U(8.W), io.downOut.fire & txCnt === 0.U ),
( isRplTimeStamp & ( txCnt === rplCnt1 ) ) -> RegEnable(io.cReg.recoTimeStamp(15,8), 0.U(8.W), io.downOut.fire & txCnt === 0.U ),
( isRplTimeStamp & ( txCnt === rplCnt2 ) ) -> RegEnable(io.cReg.recoTimeStamp(23,16), 0.U(8.W), io.downOut.fire & txCnt === 0.U ),
( isRplTimeStamp & ( txCnt === rplCnt3 ) ) -> RegEnable(io.cReg.recoTimeStamp(31,24), 0.U(8.W), io.downOut.fire & txCnt === 0.U ),
( isRplTimeStamp & ( txCnt === rplCnt4 ) ) -> RegEnable(io.cReg.recoTimeStamp(39,32), 0.U(8.W), io.downOut.fire & txCnt === 0.U ),
( isRplTimeStamp & ( txCnt === rplCnt5 ) ) -> RegEnable(io.cReg.recoTimeStamp(47,40), 0.U(8.W), io.downOut.fire & txCnt === 0.U ),
( isRplTimeStamp & ( txCnt === rplCnt6 ) ) -> RegEnable(io.cReg.recoTimeStamp(55,48), 0.U(8.W), io.downOut.fire & txCnt === 0.U ),
( isRplTimeStamp & ( txCnt === rplCnt7 ) ) -> RegEnable(io.cReg.recoTimeStamp(63,56), 0.U(8.W), io.downOut.fire & txCnt === 0.U ),
( isRplDeltaStamp & ( txCnt === rplCnt8 ) ) -> io.cReg.mstDeltaTime(7,0),
( isRplDeltaStamp & ( txCnt === rplCnt9 ) ) -> io.cReg.mstDeltaTime(15,8),
( isRplDeltaStamp & ( txCnt === rplCnt10 ) ) -> io.cReg.mstDeltaTime(23,16),
@@ -137,7 +136,7 @@ abstract class MasterParserBase extends Module with RequireAsyncReset{
val recCrcCheck = Reg(UInt(32.W))
val recCrcCheck = RegInit(0.U(32.W))
when( io.req ){
rxCnt := 0.U
@@ -205,12 +204,12 @@ trait MasterParserStat{ this: MasterParserBase =>
class MasterParser extends MasterParserBase
with MasterParserStat{
val deltaTimeStamp = Reg(UInt(32.W))
val deltaTimeStamp = RegInit(0.U(32.W))
// dontTouch(deltaTimeStamp)
io.deltaTimeStamp := deltaTimeStamp
val txStamps = Reg(UInt(32.W))
val pkgChkCnt = Reg(UInt(4.W))
val txStamps = RegInit(0.U(32.W))
val pkgChkCnt = RegInit(0.U(4.W))
when( io.upIn.fire & io.upIn.bits.tlast ){
pkgChkCnt := 0.U

214
src/main/scala/backBoard/shin/MstSlvSwitch.scala
View File

@@ -32,6 +32,7 @@ class TopBase_IO_Bundle extends Bundle{
val bias = Output(UInt(2.W))
val spiSel = Output(UInt(2.W))
val isPllCfg = Output(Bool())
}
@@ -57,9 +58,15 @@ abstract class MstSlvSwitchBase extends Module with RequireAsyncReset{
val slaveParser = Module(new SlaveParser )
val masterParser = Module(new MasterParser)
val b4b5DownEncoder = Module(new b4b5DualEncode)
val b4b5DownDecoder = Module(new b4b5DualDecode)
val b4b5UpEncoder = Module(new b4b5DualEncode)
val b4b5UpDecoder = Module(new b4b5DualDecode)
val b8b10DownEncoder = Module(new b8b10Encode)
val b8b10DownDecoder = Module(new b8b10Decode)
val b8b10UpEncoder = Module(new b8b10Encode)
val b8b10UpDecoder = Module(new b8b10Decode)
val interface = Module(new Interface)
@@ -91,7 +98,8 @@ abstract class MstSlvSwitchBase extends Module with RequireAsyncReset{
io.refTop := interface.io.cReg.refTop
io.bias := interface.io.cReg.bias
io.spiSel := interface.io.cReg.spiSel
io.spiSel := interface.io.cReg.spiSel
io.isPllCfg := interface.io.isPllCfg
val sram = Seq(
for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },
@@ -118,13 +126,24 @@ abstract class MstSlvSwitchBase extends Module with RequireAsyncReset{
val lvdsSMEnq = for( i <- 0 until 4 ) yield WireDefault(false.B); interface.io.lvdsSMEnq := lvdsSMEnq
val lvdsSMDeq = for( i <- 0 until 4 ) yield WireDefault(false.B); interface.io.lvdsSMDeq := lvdsSMDeq
val lvdsSMComf = for( i <- 0 until 4 ) yield WireDefault(false.B)
val lvdsSMAbrt = for( i <- 0 until 4 ) yield WireDefault(false.B)
smUnit(0).io.enq := lvdsSMEnq(0)
smUnit(2).io.enq := lvdsSMEnq(1)
smUnit(4).io.enq := lvdsSMEnq(2)
smUnit(6).io.enq := lvdsSMEnq(3)
smUnit(0).io.isComf := lvdsSMComf(0)
smUnit(2).io.isComf := lvdsSMComf(1)
smUnit(4).io.isComf := lvdsSMComf(2)
smUnit(6).io.isComf := lvdsSMComf(3)
smUnit(0).io.isAbrt := lvdsSMAbrt(0)
smUnit(2).io.isAbrt := lvdsSMAbrt(1)
smUnit(4).io.isAbrt := lvdsSMAbrt(2)
smUnit(6).io.isAbrt := lvdsSMAbrt(3)
smUnit(1).io.deq := lvdsSMDeq(0)
smUnit(3).io.deq := lvdsSMDeq(1)
smUnit(5).io.deq := lvdsSMDeq(2)
@@ -151,6 +170,16 @@ abstract class MstSlvSwitchBase extends Module with RequireAsyncReset{
smUnit(5).io.enq := interface.io.uSMenq(2)
smUnit(7).io.enq := interface.io.uSMenq(3)
smUnit(1).io.isComf := RegNext( smUnit(1).io.enq, false.B )
smUnit(3).io.isComf := RegNext( smUnit(3).io.enq, false.B )
smUnit(5).io.isComf := RegNext( smUnit(5).io.enq, false.B )
smUnit(7).io.isComf := RegNext( smUnit(7).io.enq, false.B )
smUnit(1).io.isAbrt := false.B
smUnit(3).io.isAbrt := false.B
smUnit(5).io.isAbrt := false.B
smUnit(7).io.isAbrt := false.B
for( i <- 0 until 8 ){
interface.io.smUsedDepth(i) := smUnit(i).io.cnt
smUnit(i).io.flush := interface.io.isSMReset(i)
@@ -255,7 +284,6 @@ abstract class MstSlvSwitchBase extends Module with RequireAsyncReset{
}
trait MstSlvSwitchMaster{ this: MstSlvSwitchBase =>
when( interface.io.cReg.modeSel === true.B ){
@@ -267,16 +295,24 @@ trait MstSlvSwitchMaster{ this: MstSlvSwitchBase =>
when( interface.io.txReq.bits.rxSM === 0.U ){
smUnit(0).io.sram_w := masterParser.io.sram_w
lvdsSMEnq(0) := masterParser.io.rxEnq
lvdsSMEnq(0) := masterParser.io.rxEnq
lvdsSMComf(0) := RegNext(masterParser.io.rxEnq, false.B)
lvdsSMAbrt(0) := false.B
} .elsewhen( interface.io.txReq.bits.rxSM === 1.U ){
smUnit(2).io.sram_w := masterParser.io.sram_w
lvdsSMEnq(1) := masterParser.io.rxEnq
lvdsSMEnq(1) := masterParser.io.rxEnq
lvdsSMComf(1) := RegNext(masterParser.io.rxEnq, false.B)
lvdsSMAbrt(1) := false.B
} .elsewhen( interface.io.txReq.bits.rxSM === 2.U ){
smUnit(4).io.sram_w := masterParser.io.sram_w
lvdsSMEnq(2) := masterParser.io.rxEnq
lvdsSMEnq(2) := masterParser.io.rxEnq
lvdsSMComf(2) := RegNext(masterParser.io.rxEnq, false.B)
lvdsSMAbrt(2) := false.B
} .elsewhen( interface.io.txReq.bits.rxSM === 3.U ){
smUnit(6).io.sram_w := masterParser.io.sram_w
lvdsSMEnq(3) := masterParser.io.rxEnq
lvdsSMEnq(3) := masterParser.io.rxEnq
lvdsSMComf(3) := RegNext(masterParser.io.rxEnq, false.B)
lvdsSMAbrt(3) := false.B
}
when( interface.io.txReq.bits.txSM === 0.U ){
@@ -344,6 +380,16 @@ trait MstSlvSwitchSlave{ this: MstSlvSwitchBase =>
lvdsSMEnq(2) := slaveParser.io.dSMenq(2)
lvdsSMEnq(3) := slaveParser.io.dSMenq(3)
lvdsSMComf(0) := slaveParser.io.downRecStat.isFinish
lvdsSMComf(1) := slaveParser.io.downRecStat.isFinish
lvdsSMComf(2) := slaveParser.io.downRecStat.isFinish
lvdsSMComf(3) := slaveParser.io.downRecStat.isFinish
lvdsSMAbrt(0) := slaveParser.io.downRecStat.isRecError
lvdsSMAbrt(1) := slaveParser.io.downRecStat.isRecError
lvdsSMAbrt(2) := slaveParser.io.downRecStat.isRecError
lvdsSMAbrt(3) := slaveParser.io.downRecStat.isRecError
lvdsSMDeq(0) := slaveParser.io.uSMdeq(0)
lvdsSMDeq(1) := slaveParser.io.uSMdeq(1)
lvdsSMDeq(2) := slaveParser.io.uSMdeq(2)
@@ -373,10 +419,10 @@ trait MstSlvSwitchSlave{ this: MstSlvSwitchBase =>
slaveParser.io.intHWClr(0) := interface.io.intHWTrig(0) & interface.io.intHWClr(0)
slaveParser.io.intHWClr(1) := interface.io.intHWTrig(1) & interface.io.intHWClr(1)
io.downCDRIn.flush := RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0) )
io.upCDRIn.flush := RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1) )
io.downCDROut.flush := RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0) )
io.upCDROut.flush := RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1) )
io.downCDRIn.flush := RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0), false.B )
io.upCDRIn.flush := RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1), false.B )
io.downCDROut.flush := RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0), false.B )
io.upCDROut.flush := RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1), false.B )
interface.io.lvds <> slaveParser.io.lvds
@@ -396,7 +442,7 @@ trait MstSlvSwitchWatchDog{ this: MstSlvSwitchBase =>
//看门狗1~16，SM监控
val isWdtSMEnable = for( _ <- 0 until 16 ) yield { RegInit(false.B) }
val wdtSMCnt = for( _ <- 0 until 16 ) yield { Reg(UInt(32.W)) }
val wdtSMCnt = for( _ <- 0 until 16 ) yield { RegInit(0.U(32.W)) }
for( i <- 0 until 8 ){
when( smUnit(i).io.enq ){
@@ -426,7 +472,7 @@ trait MstSlvSwitchWatchDog{ this: MstSlvSwitchBase =>
//看门狗0 发送后回包是否超时
val isWdtRec2RtnEnable = RegInit(false.B)
val wdtRec2RtnCnt = Reg(UInt(32.W))
val wdtRec2RtnCnt = RegInit(0.U(32.W))
when(
(io.upCDRIn.axis.fire & io.upCDRIn.axis.bits.tlast) |
@@ -448,7 +494,7 @@ trait MstSlvSwitchWatchDog{ this: MstSlvSwitchBase =>
interface.io.wdtTrigger(0) := wdtRec2RtnCnt === interface.io.cReg.wdtTarCnt(0)
//看门狗17
val wdtRec2RecCnt = Reg(UInt(32.W))
val wdtRec2RecCnt = RegInit(0.U(32.W))
when( interface.io.cReg.wdtEnable.extract(17) & (wdtRec2RecCnt < interface.io.cReg.wdtTarCnt(17)) ){
wdtRec2RecCnt := wdtRec2RecCnt + 1.U
@@ -464,45 +510,119 @@ trait MstSlvSwitchWatchDog{ this: MstSlvSwitchBase =>
}
trait MstSlvSwitchDataPath{ this: MstSlvSwitchBase =>
val isDwUpEx = interface.io.cReg.dwupEx(15,8) === "h58".U && interface.io.cReg.dwupEx.extract(0)
when( ~isDwUpEx ){ //未交叉
when( interface.io.cReg.modeSel === false.B ){ //slave
when( (slaveParser.io.intHWTrig(0) | slaveParser.io.intHWTrig(1)) | interface.io.isPoReset ){ //硬件错误
io.downCDRIn.serDat := false.B
io.upCDRIn.serDat := false.B
when( slaveParser.io.isLoop ){ //回环
io.dDatOut := false.B
io.uDatOut := io.dDatIn
} .otherwise{ //非回环
io.dDatOut := io.dDatIn
io.uDatOut := io.uDatIn
}
} .otherwise{ //无硬件错误
when( slaveParser.io.isLoop ){ //回环
io.downCDRIn.serDat := io.dDatIn
io.upCDRIn.serDat := io.downCDROut.serDat
io.dDatOut := false.B
io.uDatOut := io.upCDROut.serDat
} .otherwise{ //非回环
io.downCDRIn.serDat := io.dDatIn
io.upCDRIn.serDat := io.uDatIn
io.dDatOut := io.downCDROut.serDat
io.uDatOut := io.upCDROut.serDat
}
}
} .otherwise{ //master
io.downCDRIn.serDat := false.B
io.upCDRIn.serDat := io.uDatIn
io.dDatOut := io.downCDROut.serDat
io.uDatOut := false.B
}
} .otherwise{ //交叉
when( interface.io.cReg.modeSel === false.B ){ //slave
when( (slaveParser.io.intHWTrig(0) | slaveParser.io.intHWTrig(1)) | interface.io.isPoReset ){ //硬件错误
when( slaveParser.io.isLoop ){ //回环
io.dDatOut := io.uDatIn
io.uDatOut := false.B
io.downCDRIn.serDat := false.B
io.upCDRIn.serDat := false.B
} .otherwise{ //非回环
io.dDatOut := io.dDatIn
io.uDatOut := io.uDatIn
io.downCDRIn.serDat := false.B
io.upCDRIn.serDat := false.B
}
} .otherwise{ //无硬件错误
when( slaveParser.io.isLoop ){ //回环
io.downCDRIn.serDat := io.uDatIn
io.upCDRIn.serDat := io.downCDROut.serDat
io.uDatOut := false.B
io.dDatOut := io.upCDROut.serDat
} .otherwise{ //非回环
io.downCDRIn.serDat := io.uDatIn
io.upCDRIn.serDat := io.dDatIn
io.dDatOut := io.upCDROut.serDat
io.uDatOut := io.downCDROut.serDat
}
}
} .otherwise{ //master
io.downCDRIn.serDat := false.B
io.upCDRIn.serDat := io.dDatIn
io.uDatOut := io.downCDROut.serDat
io.dDatOut := false.B
}
}
}
trait MstSlvSwitchB8B4{ this: MstSlvSwitchBase =>
val isUsing8b10b = interface.io.cReg.b8b4Sel(15,8) === "h59".U && interface.io.cReg.b8b4Sel.extract(0)
when( isUsing8b10b ){
b8b10DownEncoder.io <> io.downCDROut.encode
b8b10DownDecoder.io <> io.downCDRIn.decode
b8b10UpEncoder.io <> io.upCDROut.encode
b8b10UpDecoder.io <> io.upCDRIn.decode
b4b5DownEncoder.io.isEnable := false.B
b4b5DownEncoder.io.dataIn := 0.U
b4b5DownDecoder.io.dataIn := 0.U
b4b5UpEncoder.io.isEnable := false.B
b4b5UpEncoder.io.dataIn := 0.U
b4b5UpDecoder.io.dataIn := 0.U
} .otherwise{
b4b5DownEncoder.io <> io.downCDROut.encode
b4b5DownDecoder.io <> io.downCDRIn.decode
b4b5UpEncoder.io <> io.upCDROut.encode
b4b5UpDecoder.io <> io.upCDRIn.decode
b8b10DownEncoder.io.isEnable := false.B
b8b10DownEncoder.io.dataIn := 0.U
b8b10DownDecoder.io.dataIn := 0.U
b8b10UpEncoder.io.isEnable := false.B
b8b10UpEncoder.io.dataIn := 0.U
b8b10UpDecoder.io.dataIn := 0.U
}
}
class MstSlvSwitch extends MstSlvSwitchBase
with MstSlvSwitchMaster
with MstSlvSwitchSlave
with MstSlvSwitchWatchDog{
with MstSlvSwitchWatchDog
with MstSlvSwitchDataPath
with MstSlvSwitchB8B4{
when( interface.io.cReg.modeSel === false.B ){ //slave
when( (slaveParser.io.intHWTrig(0) | slaveParser.io.intHWTrig(1)) | interface.io.isPoReset ){ //硬件错误
io.downCDRIn.serDat := false.B
io.upCDRIn.serDat := false.B
when( slaveParser.io.isLoop ){ //回环
io.dDatOut := false.B
io.uDatOut := io.dDatIn
} .otherwise{ //非回环
io.dDatOut := io.dDatIn
io.uDatOut := io.uDatIn
}
} .otherwise{ //无硬件错误
when( slaveParser.io.isLoop ){ //回环
io.downCDRIn.serDat := io.dDatIn
io.upCDRIn.serDat := io.downCDROut.serDat
io.dDatOut := false.B
io.uDatOut := io.upCDROut.serDat
} .otherwise{ //非回环
io.downCDRIn.serDat := io.dDatIn
io.upCDRIn.serDat := io.uDatIn
io.dDatOut := io.downCDROut.serDat
io.uDatOut := io.upCDROut.serDat
}
}
} .otherwise{ //master
io.downCDRIn.serDat := false.B
io.upCDRIn.serDat := io.uDatIn
io.dDatOut := io.downCDROut.serDat
io.uDatOut := false.B
}

24
src/main/scala/backBoard/shin/SMUnit.scala
View File

@@ -34,7 +34,8 @@ class SMUnitIO(depth: Int) extends Bundle {
val cnt = Output(UInt(8.W))
val flush = Input(Bool())
val isComf = Input(Bool())
val isAbrt = Input(Bool())
}
abstract class SMUnitBase(depth: Int = 4) extends Module with RequireAsyncReset{
@@ -43,16 +44,18 @@ abstract class SMUnitBase(depth: Int = 4) extends Module with RequireAsyncReset{
val wPtr = RegInit(0.U((log2Ceil(depth)+1).W))
val rPtr = RegInit(0.U((log2Ceil(depth)+1).W))
val cPtr = RegInit(0.U((log2Ceil(depth)+1).W))
val isFull = (wPtr ^ rPtr) === (1.U << log2Ceil(depth))
val isEmpty = ( wPtr === rPtr )
val isEmpty = ( cPtr === rPtr )
when(io.flush){
wPtr := 0.U
} .elsewhen( io.enq & ~isFull ){
wPtr := wPtr + 1.U
// assert( ~isFull)
} .elsewhen( io.isAbrt ){
wPtr := cPtr
}
when(io.flush){
@@ -82,24 +85,19 @@ abstract class SMUnitBase(depth: Int = 4) extends Module with RequireAsyncReset{
}
}
io.sram_r.datar := Mux1H( ( 0 until depth).map{ i =>
( (rPtr(log2Ceil(depth)-1, 0)) === i.U ) -> io.sram(i).rd.datar
})
val cnt = RegInit(0.U((log2Ceil(depth+1)).W)); io.cnt := cnt
io.cnt := cPtr - rPtr
when( io.flush ){
cnt := 0.U
} .elsewhen( io.enq & ~isFull ){
cnt := cnt + 1.U
assert(cnt =/= depth.U)
} .elsewhen( io.deq & ~isEmpty ){
cnt := cnt - 1.U
assert(cnt =/= 0.U)
cPtr := 0.U
} .elsewhen( io.isComf ){
cPtr := wPtr
}
}
class SMUnit(depth: Int = 4) extends SMUnitBase(depth) {

56
src/main/scala/backBoard/shin/SlaveParser.scala
View File

@@ -187,11 +187,10 @@ abstract class SlaveParserBase extends Module with RequireAsyncReset{
//接收子报文
val downSubMsgHeadInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTxInfo) } //子报文头
val upSubMsgHeadInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTxInfo) }
val downSubMsgTailInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTail) } //子报文头
val upSubMsgTailInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTail) }
val downSubMsgHeadInfo = for( _ <- 0 until 2 ) yield { RegInit(0.U.asTypeOf(new SubMsgTxInfo)) } //子报文头
val upSubMsgHeadInfo = for( _ <- 0 until 2 ) yield { RegInit(0.U.asTypeOf(new SubMsgTxInfo)) }
val downSubMsgTailInfo = for( _ <- 0 until 2 ) yield { RegInit(0.U.asTypeOf(new SubMsgTail) ) } //子报文头
val upSubMsgTailInfo = for( _ <- 0 until 2 ) yield { RegInit(0.U.asTypeOf(new SubMsgTail) ) }
val downRecFifo = for( _ <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 20)) } //子报文负载
@@ -485,9 +484,9 @@ trait SlaveParserRW{ this: SlaveParserBase =>
//写入 SM或寄存器空间
val addrw = Reg(UInt(15.W))
val addrw = RegInit(0.U(15.W))
val logicAddrwNext = Wire( UInt(30.W) )
val logicAddrw = RegNext(logicAddrwNext)
val logicAddrw = RegNext(logicAddrwNext, 0.U(30.W))
val isWRReg = (addrw(14,11) === "b0000".U)
val isWRSM0 = (addrw(14,11) === "b0001".U)
@@ -625,9 +624,9 @@ trait SlaveParserRW{ this: SlaveParserBase =>
val upTransLenCnt = RegInit(0.U)
val addrr = Reg(UInt(15.W))
val addrr = RegInit(0.U(15.W))
val logicAddrrNext = Wire( UInt(30.W) )
val logicAddrr = RegNext(logicAddrrNext)
val logicAddrr = RegNext(logicAddrrNext, 0.U(30.W))
val isUpLgcAddrrAcquireTrans = //是否触发地址转换
@@ -697,14 +696,14 @@ trait SlaveParserRW{ this: SlaveParserBase =>
( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR ) ) |
(~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR ) )
)
) & ( (RegNext(upRecParser.io.stateCurr) =/= STATE_PAYLOAD_DATA) | upRecParser.io.data.fire )
) & ( (RegNext(upRecParser.io.stateCurr, STATE_IDLE) =/= STATE_PAYLOAD_DATA) | upRecParser.io.data.fire )
val isLgcRead =
((upRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & (
( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( (upSubMsgHeadInfo(0).isLgcIndex & upTransLenCnt =/= 0.U ) )) |
(~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( (upSubMsgHeadInfo(1).isLgcIndex & upTransLenCnt =/= 0.U ) ))
)
) & ( RegNext(isUpLgcAddrrAcquireTrans) | upRecParser.io.data.fire )
) & ( RegNext(isUpLgcAddrrAcquireTrans, false.B) | upRecParser.io.data.fire )
val isLvdsEnR = isSeqRead | isLgcRead
@@ -840,20 +839,15 @@ trait SlaveParserSync{ this: SlaveParserBase =>
val downTimeStamp = Reg(UInt(64.W)) //下行本地时间戳寄存器
val upTimeStamp = Reg(UInt(64.W)) //上行本地时间戳寄存器
val mstTimeStamp = Reg(UInt(64.W)) //主站时间戳
val mstDeltaTimeStamp = Reg(UInt(32.W)); io.mstDeltaTimeStamp := mstDeltaTimeStamp //主站时间戳差值
val slvDeltaTimeStamp = Reg(UInt(32.W)); io.slvDeltaTime := slvDeltaTimeStamp //从站时间戳差值
val downTimeStamp = RegInit(0.U(64.W)) //下行本地时间戳寄存器
val upTimeStamp = RegInit(0.U(64.W)) //上行本地时间戳寄存器
val mstTimeStamp = RegInit(0.U(64.W)) //主站时间戳
val mstDeltaTimeStamp = RegInit(0.U(32.W)); io.mstDeltaTimeStamp := mstDeltaTimeStamp //主站时间戳差值
val slvDeltaTimeStamp = RegInit(0.U(32.W)); io.slvDeltaTime := slvDeltaTimeStamp //从站时间戳差值
val mstSlvDeltaTimeStamp = Reg(UInt(64.W)) //主发从接时间差(中间变量)
val deltaMstSlvDeltaTimeStamp = Reg(UInt(64.W)) //主差从差时间差(中间变量)
val deltaFinal = Reg(UInt(64.W)); io.deltaFinal := deltaFinal //当前时间戳与主站时间差
// val recoTimeStamp = Reg(UInt(64.W)) //时钟补偿寄存器
// dontTouch(recoTimeStamp)
val mstSlvDeltaTimeStamp = RegInit(0.U(64.W)) //主发从接时间差(中间变量)
val deltaMstSlvDeltaTimeStamp = RegInit(0.U(64.W)) //主差从差时间差(中间变量)
val deltaFinal = RegInit(0.U(64.W)); io.deltaFinal := deltaFinal //当前时间戳与主站时间差
// recoTimeStamp = io.timeStamp + deltaFinal
// recoTimeStamp = io.timeStamp + mstSlvDeltaTimeStamp + deltaMstSlvDeltaTimeStamp
@@ -883,7 +877,7 @@ trait SlaveParserSync{ this: SlaveParserBase =>
( ~isDownRecPing & downSubMsgHeadInfo(1).devIndex === 0.U & downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_SYNC )
)
val syncCnt = Reg(UInt(4.W))
val syncCnt = RegInit(0.U(4.W))
when( downRecParser.io.rec.fire ){
when( isSync ){
@@ -931,7 +925,7 @@ trait SlaveParserSync{ this: SlaveParserBase =>
}
}
when( RegNext(isSync) & ~isSync ){
when( RegNext(isSync, false.B) & ~isSync ){
// deltaMstSlvDeltaTimeStamp := (mstDeltaTimeStamp - slvDeltaTimeStamp) >>> 1 //(mstDeltaTimeStamp - slvDeltaTimeStamp) >> 1
addr64_op1 := Cat( Fill(32, mstDeltaTimeStamp(31)), mstDeltaTimeStamp) //组合逻辑
@@ -939,7 +933,7 @@ trait SlaveParserSync{ this: SlaveParserBase =>
addrConflict(2) := true.B //组合逻辑
deltaMstSlvDeltaTimeStamp := Cat(addr64_res(63),addr64_res(63,1)) //时序逻辑
} .elsewhen( RegNext(RegNext(isSync)) & ~RegNext(isSync) ){
} .elsewhen( RegNext(RegNext(isSync, false.B), false.B) & ~RegNext(isSync, false.B) ){
// deltaFinal := mstSlvDeltaTimeStamp + deltaMstSlvDeltaTimeStamp
addr64_op1 := mstSlvDeltaTimeStamp //组合逻辑
addr64_op2 := deltaMstSlvDeltaTimeStamp //组合逻辑
@@ -1020,11 +1014,11 @@ with SlaveParserProbe{
io.intHWTrig(0) := downRecParser.io.isError
io.intHWTrig(1) := upRecParser.io.isError
downRecParser.io.flush := RegNext(downRecParser.io.isError & io.intHWClr(0))
downSendGen.io.flush := RegNext(downRecParser.io.isError & io.intHWClr(0))
downRecParser.io.flush := RegNext(downRecParser.io.isError & io.intHWClr(0), false.B)
downSendGen.io.flush := RegNext(downRecParser.io.isError & io.intHWClr(0), false.B)
upRecParser.io.flush := RegNext(upRecParser.io.isError & io.intHWClr(1))
upSendGen.io.flush := RegNext(upRecParser.io.isError & io.intHWClr(1))
upRecParser.io.flush := RegNext(upRecParser.io.isError & io.intHWClr(1), false.B)
upSendGen.io.flush := RegNext(upRecParser.io.isError & io.intHWClr(1), false.B)
io.downRecStat := downRecParser.io.stat
io.upRecStat := upRecParser.io.stat

12
src/main/scala/backBoard/shin/SlaveRecParser.scala
View File

@@ -55,7 +55,7 @@ class SlaveRecParser extends Module with RequireAsyncReset{
crc.io.flush := stateCurr === STATE_IDLE | io.flush
val crcData = Reg(UInt(32.W))
val crcData = RegInit(0.U(32.W))
val isCrcPass = crc.io.crc === Cat( crcData(23,0), io.rec.bits.tdata )
when( io.rec.fire & stateCurr === STATE_CRC ){
@@ -72,12 +72,12 @@ class SlaveRecParser extends Module with RequireAsyncReset{
val lengthCnt = RegInit(0.U(12.W)) //动态计数器
val frameLenCnt = Reg(UInt(12.W)) //帧长度计数
val frameLenCnt = RegInit(0.U(12.W)) //帧长度计数
io.frameReq.valid := (stateCurr === STATE_HEADER) & (stateNext === STATE_SUBMSG_HEADER | stateNext === STATE_CRC)
val frameHeader = Reg(new FrameHeader)
val frameHeader = RegInit(0.U.asTypeOf(new FrameHeader))
io.frameReq.bits.frameLenAim := frameHeader.frameLenAim
io.frameReq.bits.frameStyle := frameHeader.frameStyle
io.frameReq.bits.frameInfo := frameHeader.frameInfo | io.rec.bits.tdata
@@ -85,8 +85,8 @@ class SlaveRecParser extends Module with RequireAsyncReset{
io.subMsgHeadReq.valid := (stateCurr === STATE_SUBMSG_HEADER) & (stateNext === STATE_PAYLOAD_DATA)
io.subMsgTailReq.valid := (stateCurr === STATE_SUBMSG_TAIL) & (stateNext =/= STATE_SUBMSG_TAIL)
val subMsgHeader = Reg(new SubMsgHeader)
val subMsgTail = Reg(new SubMsgTail)
val subMsgHeader = RegInit(0.U.asTypeOf(new SubMsgHeader))
val subMsgTail = RegInit(0.U.asTypeOf(new SubMsgTail))
io.subMsgHeadReq.bits.devIndex := subMsgHeader.devIndex
io.subMsgHeadReq.bits.style := subMsgHeader.style
@@ -182,7 +182,7 @@ class SlaveRecParser extends Module with RequireAsyncReset{
Mux( io.flush, STATE_IDLE,
Mux1H(Seq(
//必须使用上升沿触发，以避免前一帧长度超过预期
( stateCurr === STATE_IDLE ) -> Mux( ~RegNext(io.rec.valid) & io.rec.valid, STATE_HEADER, STATE_IDLE ),
( stateCurr === STATE_IDLE ) -> Mux( ~RegNext(io.rec.valid, false.B) & io.rec.valid, STATE_HEADER, STATE_IDLE ),
( stateCurr === STATE_HEADER ) -> Mux( io.rec.fire, Mux(io.rec.bits.tlast, STATE_ERROR,
Mux( lengthCnt === (4-1).U,
MuxCase( STATE_ERROR, Array(

10
src/main/scala/backBoard/shin/SlaveSendGen.scala
View File

@@ -66,10 +66,10 @@ class SlaveSendGen extends Module with RequireAsyncReset{
val frameInfo = Reg(new FrameHeader)
val frameInfo = RegInit(0.U.asTypeOf(new FrameHeader))
val subMsgHeadInfo = Reg(new SubMsgTxInfo)
val subMsgTailInfo = Reg(new SubMsgTail)
val subMsgHeadInfo = RegInit(0.U.asTypeOf(new SubMsgTxInfo))
val subMsgTailInfo = RegInit(0.U.asTypeOf(new SubMsgTail))
@@ -88,8 +88,8 @@ class SlaveSendGen extends Module with RequireAsyncReset{
val lengthCnt = Reg(UInt(12.W))
val frameLenCnt = Reg(UInt(12.W))
val lengthCnt = RegInit(0.U(12.W))
val frameLenCnt = RegInit(0.U(12.W))
when( io.send.fire ){
when( stateCurr === STATE_FRAME_HEADER ){

18
src/main/scala/backBoard/shin/SpiInterface.scala
View File

@@ -46,20 +46,20 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
val isSckNegedge = shiftSCK(2) & ~shiftSCK(1) //确定下降沿放数据到数据线上
val exRego = Reg(UInt(8.W))
val exRegi = Reg(UInt(8.W))
val exRego = RegInit(0.U(8.W))
val exRegi = RegInit(0.U(8.W))
val addrw = RegInit(0.U(16.W))
val addrr = RegInit(0.U(16.W))
val spiCmd = Reg(UInt(8.W))
val spiCmd = RegInit(0.U(8.W))
val isSpiWrite = spiCmd === 0.U
val isSpiRead = spiCmd === 1.U
val bitSel = Reg(UInt(3.W))
val byteSel = Reg(UInt(12.W))
val bitSel = RegInit(0.U(3.W))
val byteSel = RegInit(0.U(12.W))
io.isEnR :=
@@ -69,9 +69,7 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
io.dataw := exRegi
io.addrr := Mux( isSpiRead, addrr + 1.U, addrr )
io.addrw := addrw
// io.addrSel :=
// Mux( isSpiRead, addrSel + 1.U, addrSel )//覆盖三种情况
// val readData = RegEnable(io.datar, io.isEnR)
when( shiftCSn(2) & ~shiftCSn(1) ){
@@ -133,7 +131,7 @@ class SSpiInterface extends SpiInterfaceBase{
bitSel := bitSel + 1.U
}
val shiftMOSI = ShiftRegisters(spi.mosi, 3)
val shiftMOSI = ShiftRegisters(spi.mosi, 3, false.B, true.B)
//输入看SCK上升沿
when( isSckPosedge & ~shiftCSn(1) ){
@@ -174,7 +172,7 @@ class QSpiInterface extends SpiInterfaceBase{
bitSel := ~bitSel
}
val shiftMOSI = ShiftRegisters(qspi.mosi, 3)
val shiftMOSI = ShiftRegisters(qspi.mosi, 3, 0.U(4.W), true.B)

106
src/test/scala/SimCDR.scala Normal file
View File

@@ -0,0 +1,106 @@
package BACK
import chisel3._
import chisel3.util._
class SimCDR extends Module with RequireAsyncReset{
val io = IO(new Bundle{
val data = Input( UInt(8.W) )
val multiCLK = Input(Vec(16, Bool()))
val flush = Input(Bool())
val isSuccess = Output(Bool())
val isFailed = Output(Bool())
})
val cdrIn = Module(new MPCDRIn)
val cdrOut = Module(new CDROut)
val record = Module( new Queue(UInt(8.W), 256) )
val dataCnt = RegInit(0.U(12.W))
val payloadLen = RegInit(("hFFF".U)(12.W))
val b4b5Encoder = Module(new b4b5DualEncode)
val b4b5Decoder = Module(new b4b5DualDecode)
val b8b10Encoder = Module(new b8b10Encode)
val b8b10Decoder = Module(new b8b10Decode)
when( cdrOut.io.axis.fire & dataCnt === 0.U ){
payloadLen := Cat( io.data, 0.U(4.W) )
} .elsewhen( cdrOut.io.axis.fire & dataCnt === 1.U ){
payloadLen := Cat( payloadLen(11,4), io.data(7,4) ) + 4.U + 4.U
}
when( cdrOut.io.axis.fire ){
when( dataCnt >= payloadLen - 1.U ){
dataCnt := 0.U
} .otherwise{
dataCnt := dataCnt + 1.U
}
}
cdrOut.io.flush := io.flush
cdrIn.clock := io.multiCLK(0).asClock
cdrIn.io.flush := io.flush
cdrIn.multiCLK := io.multiCLK
cdrIn.io.serDat := cdrOut.io.serDat
assert( ~(record.io.enq.valid & ~record.io.enq.ready), "Assert Failed, Warning, fifo overflow!\n" )
assert( ~(~record.io.deq.valid & record.io.deq.ready), "Assert Failed, Warning, fifo underflow!\n" )
val isTxEnd = cdrOut.io.axis.fire & cdrOut.io.axis.bits.tlast
cdrOut.io.axis.valid := ~io.flush & ShiftRegisters( ~isTxEnd, 16 ).reduce(_&_)
cdrOut.io.axis.bits.tdata := io.data
cdrOut.io.axis.bits.tuser := false.B
cdrOut.io.axis.bits.tlast := dataCnt === (payloadLen - 1.U)
record.io.enq.valid := cdrOut.io.axis.fire
record.io.enq.bits := io.data
record.io.deq.ready := cdrIn.io.axis.fire
cdrIn.io.axis.ready := true.B
io.isFailed := cdrIn.io.axis.fire & (record.io.deq.bits =/= cdrIn.io.axis.bits.tdata)
io.isSuccess := cdrIn.io.axis.fire & cdrIn.io.axis.bits.tlast
val isUsing8b10b = true.B
when( isUsing8b10b ){
b8b10Encoder.io <> cdrOut.io.encode
b8b10Decoder.io <> cdrIn.io.decode
b4b5Encoder.io.isEnable := false.B
b4b5Encoder.io.dataIn := 0.U
b4b5Decoder.io.dataIn := 0.U
} .otherwise{
b4b5Encoder.io <> cdrOut.io.encode
b4b5Decoder.io <> cdrIn.io.decode
b8b10Encoder.io.isEnable := false.B
b8b10Encoder.io.dataIn := 0.U
b8b10Decoder.io.dataIn := 0.U
}
}

5
src/test/scala/gcd/test.scala
View File

@@ -103,6 +103,11 @@ object testShinModule extends App {
ChiselGeneratorAnnotation(() => { new ShinTop }),
))
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/SimCDR/", "-e", "verilog" ) ++ args, Seq(
ChiselGeneratorAnnotation(() => { new SimCDR }),
))
}