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优化cdrsim模式

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This commit is contained in:
RuigeLee
2025-09-15 17:47:31 +08:00
parent bffe4fcab1
commit e83ba629b7
1 changed files with 39 additions and 12 deletions
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51
src/test/scala/SimCDR.scala
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@@ -24,7 +24,6 @@ class SimCDR extends Module with RequireAsyncReset{
val cdrInSample = Module(new CDRInMultiSample(clkNum = 4))
val cdrOut = Module(new CDROut)
val record = Module( new Queue(UInt(8.W), 256) )
val dataCnt = RegInit(0.U(12.W))
val payloadLen = RegInit(("hFFF".U)(12.W))
@@ -35,7 +34,10 @@ class SimCDR extends Module with RequireAsyncReset{
val b8b10Encoder = Module(new b8b10Encode)
val b8b10Decoder = Module(new b8b10Decode)
val wPtr = RegInit(0.U(12.W))
val rPtr = withClockAndReset( io.multiCLK(0).asClock, reset ) { RegInit(0.U(12.W)) }
val asyncFifo = Module(new ShareSRAM2k)
when( cdrOut.io.axis.fire & dataCnt === 0.U ){
payloadLen := Cat( io.data, 0.U(4.W) )
@@ -57,6 +59,7 @@ class SimCDR extends Module with RequireAsyncReset{
cdrInAxis.clock := io.multiCLK(0).asClock
cdrInSample.clock := io.multiCLK(0).asClock
cdrInAxis.io.flush := io.flush
// cdrInSample.multiCLK := io.multiCLK
cdrInSample.multiCLK(0) := io.multiCLK(0)
cdrInSample.multiCLK(1) := io.multiCLK(4)
@@ -67,25 +70,21 @@ class SimCDR extends Module with RequireAsyncReset{
cdrInSample.io.serDat := cdrOut.io.serDat
assert( ~(record.io.enq.valid & ~record.io.enq.ready), "Assert Failed, Warning, fifo overflow!\n" )
assert( ~(~record.io.deq.valid & record.io.deq.ready), "Assert Failed, Warning, fifo underflow!\n" )
val isTxEnd = cdrOut.io.axis.fire & cdrOut.io.axis.bits.tlast
cdrOut.io.axis.valid := ~io.flush & ShiftRegisters( ~isTxEnd, 16 ).reduce(_&_)
cdrOut.io.axis.valid := ~io.flush & ShiftRegisters( ~isTxEnd, 32 ).reduce(_&_)
cdrOut.io.axis.bits.tdata := io.data
cdrOut.io.axis.bits.tuser := false.B
cdrOut.io.axis.bits.tlast := dataCnt === (payloadLen - 1.U)
record.io.enq.valid := cdrOut.io.axis.fire
record.io.enq.bits := io.data
record.io.deq.ready := cdrInAxis.io.axis.fire
cdrInAxis.io.axis.ready := true.B
io.isFailed := cdrInAxis.io.axis.fire & (record.io.deq.bits =/= cdrInAxis.io.axis.bits.tdata)
io.isFailed := cdrInAxis.io.axis.fire & (asyncFifo.io.datar =/= cdrInAxis.io.axis.bits.tdata)
io.isSuccess := cdrInAxis.io.axis.fire & cdrInAxis.io.axis.bits.tlast
@@ -111,10 +110,38 @@ class SimCDR extends Module with RequireAsyncReset{
}
asyncFifo.io.clockw := clock.asBool
asyncFifo.io.dataw := io.data
asyncFifo.io.addrw := wPtr(10,0)
asyncFifo.io.enw := cdrOut.io.axis.fire
asyncFifo.io.clockr := io.multiCLK(0)
asyncFifo.io.addrr := rPtr(10,0)
asyncFifo.io.enr := true.B
when( cdrOut.io.axis.fire ){
wPtr := wPtr + 1.U
}
when( cdrInAxis.io.axis.fire ){
rPtr := rPtr + 1.U
}
val isFull = (wPtr ^ rPtr) === (1.U << log2Ceil(2048))
assert(~isFull)
val coverData = RegInit(VecInit(Seq.fill(512){false.B}))
when( record.io.enq.fire ){
when( cdrOut.io.axis.fire ){
for( i <- 0 until 256 ){
when( record.io.enq.bits === i.U ){
when( io.data === i.U ){
when( b8b10Encoder.rdTest ){
coverData(i) := true.B
} .otherwise{
@@ -125,9 +152,9 @@ class SimCDR extends Module with RequireAsyncReset{
}
// val coverData = RegInit(VecInit(Seq.fill(256){false.B}))
// when( record.io.enq.fire ){
// when( cdrOut.io.axis.fire ){
// for( i <- 0 until 256 ){
// when( record.io.enq.bits === i.U ){
// when( io.data === i.U ){
// coverData(i) := true.B
// }
// }