RuigeLee
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ab0fab00fa
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物理层和链路层各自有header，需要打包两次
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2024-10-17 11:43:16 +08:00 |
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RuigeLee
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84b978cbc9
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length扩充为12bits， 取头位宽错误修复
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2024-10-16 17:31:53 +08:00 |
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RuigeLee
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0dc046bffe
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仿真开始
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2024-10-16 16:17:52 +08:00 |
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RuigeLee
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55f016d866
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编译通过。准备测试
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2024-10-16 10:49:06 +08:00 |
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RuigeLee
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a44cae1ec3
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语法清理1
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2024-10-15 17:45:42 +08:00 |
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RuigeLee
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f74cc355d4
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从站初始化逻辑写完，准备编译开始第一轮测试
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2024-10-15 17:37:53 +08:00 |
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RuigeLee
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96234875b0
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从站下行写完
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2024-10-14 17:45:39 +08:00 |
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RuigeLee
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8f9aa2d17c
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从站下行的部分逻辑
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2024-10-12 17:29:58 +08:00 |
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RuigeLee
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c605fd4efe
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shin主站逻辑代码写完，没编译
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2024-10-10 17:41:49 +08:00 |
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RuigeLee
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a6068fbda0
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新主站发送逻辑
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2024-10-09 17:37:15 +08:00 |
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RuigeLee
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58aecc043f
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led在PR为3时常亮
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2024-09-26 10:38:50 +08:00 |
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RuigeLee
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87f28c75b0
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基本稳定传输
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2024-09-24 11:19:36 +08:00 |
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RuigeLee
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753586a65e
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正确锁住，丢包率大
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2024-09-23 17:52:59 +08:00 |
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RuigeLee
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10b2e4c78f
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Revert "最后几个比特锁不住"
This reverts commit 97211f0962.
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2024-09-23 17:40:35 +08:00 |
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RuigeLee
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97211f0962
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最后几个比特锁不住
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2024-09-23 17:40:23 +08:00 |
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RuigeLee
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833ad07525
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采样头对齐问题，对齐哪个55和D5
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2024-09-23 17:23:34 +08:00 |
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RuigeLee
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6750593b48
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发送改用标志头锁时钟通道方案
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2024-09-23 16:44:44 +08:00 |
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RuigeLee
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f05e320236
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fpga测试顶层 虚拟线模式
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2024-09-20 14:56:09 +08:00 |
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RuigeLee
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3c357b54e0
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4倍频采3次
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2024-09-20 14:55:43 +08:00 |
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RuigeLee
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1368e9037d
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CDR基本测试通过
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2024-09-19 15:23:38 +08:00 |
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RuigeLee
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57c81d5cac
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CDRin编译通过
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2024-09-12 17:48:50 +08:00 |
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RuigeLee
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ba6099608c
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CDR发送测试完成
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2024-09-11 17:21:14 +08:00 |
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RuigeLee
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7350f3bcf4
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仿真，状态机错误
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2024-09-10 18:39:35 +08:00 |
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RuigeLee
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0080705f0d
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Revert "重开ebus项目"
This reverts commit a3234d7f48.
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2024-09-10 16:36:30 +08:00 |
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RuigeLee
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a3234d7f48
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重开ebus项目
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2024-09-10 16:12:18 +08:00 |
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RuigeLee
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f7697eed6b
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do的下行寄存器没有改到
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2024-09-05 15:17:20 +08:00 |
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RuigeLee
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838729a694
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新需求 din寄存器更新
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2024-09-02 17:46:14 +08:00 |
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RuigeLee
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aa5a8f9a95
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更新第15页
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2024-09-02 16:33:08 +08:00 |
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RuigeLee
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45c983acfc
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新需求 更新第15页
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2024-09-02 16:24:02 +08:00 |
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RuigeLee
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693621f1a0
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加入常数定义
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2024-07-16 15:36:40 +08:00 |
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RuigeLee
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71a489a1d0
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约束只能使用4页，留下升级空间
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2024-07-03 18:39:01 +08:00 |
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RuigeLee
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73bfd7e109
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sck下降沿操作前移到上升沿后两拍
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2024-07-03 16:36:45 +08:00 |
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RuigeLee
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17dd970d47
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上传bugfix
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2024-07-02 19:27:43 +08:00 |
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RuigeLee
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bcbaa5b39b
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spi格式修改
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2024-07-02 19:18:02 +08:00 |
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RuigeLee
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e0bfd59539
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spi面积通过
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2024-06-28 18:39:35 +08:00 |
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RuigeLee
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b696723e23
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Revert "从机上下行机制分叉"
This reverts commit a9f4fd18ab.
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2024-06-28 15:22:44 +08:00 |
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RuigeLee
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a9f4fd18ab
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从机上下行机制分叉
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2024-06-28 15:20:22 +08:00 |
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RuigeLee
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862028dac7
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dout16增加一个err灯
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2024-06-28 14:44:04 +08:00 |
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RuigeLee
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f008df4074
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SRAM规格不够大
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2024-06-28 10:27:32 +08:00 |
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RuigeLee
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5090294a12
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spi 功能测试通过，资源不足
qei 防跳变
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2024-06-27 18:47:46 +08:00 |
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RuigeLee
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eca0931fa3
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重构逻辑关系
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2024-06-26 12:31:16 +08:00 |
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RuigeLee
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f32e82cd7b
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资源节约
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2024-06-25 18:40:53 +08:00 |
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RuigeLee
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3406a418d1
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测试完成，资源超出
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2024-06-25 16:44:19 +08:00 |
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RuigeLee
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d99421cbf2
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qei准备测试
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2024-06-25 11:27:07 +08:00 |
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RuigeLee
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c40980bf2f
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等待文档更新
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2024-06-24 11:18:47 +08:00 |
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RuigeLee
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7aa7ea7ec6
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dout增加公共端IO
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2024-06-14 19:00:41 +08:00 |
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RuigeLee
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715a1e6c08
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准备QEI和Spi
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2024-06-11 18:29:02 +08:00 |
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RuigeLee
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46090a6460
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恢复ebus工程
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2024-05-24 17:32:41 +08:00 |
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RuigeLee
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b5fb27ab7c
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临时解决方案
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2024-05-24 17:31:49 +08:00 |
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RuigeLee
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7f85f14d92
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每次初始化强制清除sync,trans,uni标志位
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2024-05-23 13:45:15 +08:00 |
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