RuigeLee
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115f216139
|
moveout tx
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2023-10-08 11:34:36 +08:00 |
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RuigeLee
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3b6b3bc14b
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增加跨时钟域，准备切换分支
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2023-10-08 10:12:49 +08:00 |
|
RuigeLee
|
2435f7fa01
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rx初步优化 编译通过
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2023-10-07 16:44:13 +08:00 |
|
RuigeLee
|
fd0f1347cf
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半成品，剥离tilelinkTx，在mtx不会远大于clock；tx_FIFO不会极限小的情况下，无跨时钟保护是允许的
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2023-09-28 18:45:14 +08:00 |
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RuigeLee
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f3a35964f8
|
opt: tx/rx传输必须32比特对齐，不再支持非对齐操作
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2023-09-27 16:31:56 +08:00 |
|
RuigeLee
|
61f15c9ebe
|
bug:rx 大小端总线传输非对齐模式下mask错误
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2023-09-27 16:14:04 +08:00 |
|
RuigeLee
|
e6f34762e8
|
状态机化简
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2023-09-26 21:41:19 +08:00 |
|
RuigeLee
|
25a5c81668
|
bug: 异步复位信号缺失
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2023-09-26 21:40:47 +08:00 |
|
RuigeLee
|
51c39369c8
|
要求所有tx/rx时钟域异步复位
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2023-09-25 14:18:27 +08:00 |
|
RuigeLee
|
5ff118f527
|
rx: big-endian to little-endian
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2023-09-21 16:55:22 +08:00 |
|
RuigeLee
|
e42c6a3b11
|
dma cache to sys-port
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2023-09-20 11:17:30 +08:00 |
|
RuigeLee
|
8a9aa0436c
|
a sign for tx/rx clock merge
|
2023-09-19 18:03:30 +08:00 |
|
RuigeLee
|
4702991e69
|
tx: big-endian to little-endian
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2023-09-19 17:54:36 +08:00 |
|
RuigeLee
|
40b558d3a2
|
sync
|
2023-09-15 15:36:44 +08:00 |
|
RuigeLee
|
b098ca963e
|
test pass
|
2023-09-14 19:16:17 +08:00 |
|
RuigeLee
|
6fd836fc9c
|
new version
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2023-09-12 17:51:32 +08:00 |
|
RuigeLee
|
527f6bd761
|
fix sync misunderstanding
|
2023-09-11 17:39:19 +08:00 |
|
RuigeLee
|
05a905ac39
|
merge mirror read/write
|
2023-09-08 18:47:13 +08:00 |
|
RuigeLee
|
bf835014bc
|
16bit fsmc data; 16*2 reg, 100us
|
2023-09-08 16:37:31 +08:00 |
|
RuigeLee
|
145db92202
|
test pass
|
2023-08-31 17:39:12 +08:00 |
|
RuigeLee
|
d226487a5e
|
BUG FIX
|
2023-08-31 15:10:18 +08:00 |
|
RuigeLee
|
860e24ca99
|
check mst
|
2023-08-30 17:32:19 +08:00 |
|
RuigeLee
|
c0645cfe16
|
update sram; bug fixed; lvds failed
|
2023-08-23 19:32:41 +08:00 |
|
Ruige Lee (WSL)
|
cead446356
|
io merge
|
2023-08-22 17:50:31 +08:00 |
|
Ruige Lee (WSL)
|
44e8999ab0
|
switch from 4k to 2k
|
2023-08-22 15:32:01 +08:00 |
|
Ruige Lee (WSL)
|
704996bdfb
|
Merge branch 'main' of github.com:whutddk/RISCV-MAC-SWICH into main
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2023-08-22 14:17:55 +08:00 |
|
RuigeLee
|
a3ce58fb94
|
add fpga top
|
2023-08-21 21:14:43 +08:00 |
|
Ruige Lee (WSL)
|
37ac7817d7
|
fix sram
|
2023-08-21 14:52:21 +08:00 |
|
RuigeLee
|
5f15e94ae3
|
bug override
|
2023-08-21 11:51:59 +08:00 |
|
RuigeLee
|
31a822091b
|
Revert "devide gowin file"
This reverts commit d162b8f75c.
|
2023-08-21 11:51:25 +08:00 |
|
RuigeLee
|
d162b8f75c
|
devide gowin file
|
2023-08-21 11:46:50 +08:00 |
|
RuigeLee
|
20ddabbfb3
|
add submodule
|
2023-08-21 11:20:16 +08:00 |
|
RuigeLee
|
589fc528a0
|
compile pass
|
2023-08-20 15:50:11 +08:00 |
|
Ruige Lee
|
f3a44f0b31
|
slv
|
2023-08-18 12:10:47 +00:00 |
|
RuigeLee
|
6fa2ef5f6e
|
porta
|
2023-08-16 22:25:30 +08:00 |
|
Ruige Lee
|
bbd0f0b887
|
sync
|
2023-08-16 06:12:49 +00:00 |
|
Ruige Lee
|
6c2f0b02f8
|
FSMC
|
2023-08-15 08:42:56 +00:00 |
|
Ruige Lee
|
939fa22be5
|
wrapper of mst and slv
|
2023-08-15 02:59:10 +00:00 |
|
RuigeLee
|
3211e21e11
|
wrapper
|
2023-08-14 22:46:50 +08:00 |
|
RuigeLee
|
50403930a9
|
check chain
|
2023-08-09 16:34:29 +08:00 |
|
RuigeLee
|
1c7a226a70
|
add function demo
|
2023-08-09 14:43:24 +08:00 |
|
RuigeLee
|
68e0a6a055
|
test pass
|
2023-08-07 11:40:14 +08:00 |
|
RuigeLee
|
a041c7732a
|
over sample in spi
|
2023-08-07 10:15:56 +08:00 |
|
RuigeLee
|
d09aff40f2
|
timing close
|
2023-08-02 15:17:16 +08:00 |
|
RuigeLee
|
5d43600680
|
fpga sync
|
2023-08-01 15:50:53 +08:00 |
|
RuigeLee
|
35e6fcdb52
|
mst test pass
|
2023-08-01 14:44:05 +08:00 |
|
RuigeLee
|
24800cce9d
|
spi compile pass
|
2023-07-31 22:56:09 +08:00 |
|
RuigeLee
|
0f79860656
|
revert mdio direction
|
2023-07-31 09:19:57 +08:00 |
|
RuigeLee
|
3aa4ca17d4
|
all test pass
|
2023-07-28 20:42:35 +08:00 |
|
RuigeLee
|
2048a4d286
|
first test
|
2023-07-28 15:38:46 +08:00 |
|