RuigeLee
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3b6b3bc14b
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增加跨时钟域，准备切换分支
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2023-10-08 10:12:49 +08:00 |
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RuigeLee
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2435f7fa01
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rx初步优化 编译通过
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2023-10-07 16:44:13 +08:00 |
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RuigeLee
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fd0f1347cf
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半成品，剥离tilelinkTx，在mtx不会远大于clock；tx_FIFO不会极限小的情况下，无跨时钟保护是允许的
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2023-09-28 18:45:14 +08:00 |
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RuigeLee
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f3a35964f8
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opt: tx/rx传输必须32比特对齐，不再支持非对齐操作
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2023-09-27 16:31:56 +08:00 |
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RuigeLee
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61f15c9ebe
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bug:rx 大小端总线传输非对齐模式下mask错误
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2023-09-27 16:14:04 +08:00 |
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RuigeLee
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e6f34762e8
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状态机化简
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2023-09-26 21:41:19 +08:00 |
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RuigeLee
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25a5c81668
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bug: 异步复位信号缺失
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2023-09-26 21:40:47 +08:00 |
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RuigeLee
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51c39369c8
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要求所有tx/rx时钟域异步复位
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2023-09-25 14:18:27 +08:00 |
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RuigeLee
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5ff118f527
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rx: big-endian to little-endian
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2023-09-21 16:55:22 +08:00 |
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RuigeLee
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e42c6a3b11
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dma cache to sys-port
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2023-09-20 11:17:30 +08:00 |
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RuigeLee
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8a9aa0436c
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a sign for tx/rx clock merge
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2023-09-19 18:03:30 +08:00 |
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RuigeLee
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4702991e69
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tx: big-endian to little-endian
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2023-09-19 17:54:36 +08:00 |
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RuigeLee
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40b558d3a2
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sync
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2023-09-15 15:36:44 +08:00 |
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RuigeLee
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b098ca963e
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test pass
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2023-09-14 19:16:17 +08:00 |
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RuigeLee
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6fd836fc9c
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new version
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2023-09-12 17:51:32 +08:00 |
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RuigeLee
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527f6bd761
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fix sync misunderstanding
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2023-09-11 17:39:19 +08:00 |
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RuigeLee
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05a905ac39
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merge mirror read/write
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2023-09-08 18:47:13 +08:00 |
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RuigeLee
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bf835014bc
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16bit fsmc data; 16*2 reg, 100us
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2023-09-08 16:37:31 +08:00 |
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RuigeLee
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145db92202
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test pass
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2023-08-31 17:39:12 +08:00 |
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RuigeLee
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d226487a5e
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BUG FIX
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2023-08-31 15:10:18 +08:00 |
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RuigeLee
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860e24ca99
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check mst
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2023-08-30 17:32:19 +08:00 |
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RuigeLee
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c0645cfe16
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update sram; bug fixed; lvds failed
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2023-08-23 19:32:41 +08:00 |
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Ruige Lee (WSL)
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cead446356
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io merge
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2023-08-22 17:50:31 +08:00 |
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Ruige Lee (WSL)
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44e8999ab0
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switch from 4k to 2k
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2023-08-22 15:32:01 +08:00 |
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Ruige Lee (WSL)
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704996bdfb
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Merge branch 'main' of github.com:whutddk/RISCV-MAC-SWICH into main
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2023-08-22 14:17:55 +08:00 |
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RuigeLee
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a3ce58fb94
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add fpga top
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2023-08-21 21:14:43 +08:00 |
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Ruige Lee (WSL)
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37ac7817d7
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fix sram
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2023-08-21 14:52:21 +08:00 |
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RuigeLee
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5f15e94ae3
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bug override
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2023-08-21 11:51:59 +08:00 |
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RuigeLee
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31a822091b
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Revert "devide gowin file"
This reverts commit d162b8f75c.
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2023-08-21 11:51:25 +08:00 |
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RuigeLee
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d162b8f75c
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devide gowin file
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2023-08-21 11:46:50 +08:00 |
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RuigeLee
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20ddabbfb3
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add submodule
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2023-08-21 11:20:16 +08:00 |
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RuigeLee
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589fc528a0
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compile pass
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2023-08-20 15:50:11 +08:00 |
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Ruige Lee
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f3a44f0b31
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slv
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2023-08-18 12:10:47 +00:00 |
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RuigeLee
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6fa2ef5f6e
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porta
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2023-08-16 22:25:30 +08:00 |
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Ruige Lee
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bbd0f0b887
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sync
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2023-08-16 06:12:49 +00:00 |
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Ruige Lee
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6c2f0b02f8
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FSMC
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2023-08-15 08:42:56 +00:00 |
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Ruige Lee
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939fa22be5
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wrapper of mst and slv
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2023-08-15 02:59:10 +00:00 |
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RuigeLee
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3211e21e11
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wrapper
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2023-08-14 22:46:50 +08:00 |
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RuigeLee
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50403930a9
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check chain
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2023-08-09 16:34:29 +08:00 |
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RuigeLee
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1c7a226a70
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add function demo
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2023-08-09 14:43:24 +08:00 |
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RuigeLee
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68e0a6a055
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test pass
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2023-08-07 11:40:14 +08:00 |
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RuigeLee
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a041c7732a
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over sample in spi
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2023-08-07 10:15:56 +08:00 |
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RuigeLee
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d09aff40f2
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timing close
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2023-08-02 15:17:16 +08:00 |
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RuigeLee
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5d43600680
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fpga sync
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2023-08-01 15:50:53 +08:00 |
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RuigeLee
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35e6fcdb52
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mst test pass
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2023-08-01 14:44:05 +08:00 |
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RuigeLee
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24800cce9d
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spi compile pass
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2023-07-31 22:56:09 +08:00 |
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RuigeLee
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0f79860656
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revert mdio direction
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2023-07-31 09:19:57 +08:00 |
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RuigeLee
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3aa4ca17d4
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all test pass
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2023-07-28 20:42:35 +08:00 |
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RuigeLee
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2048a4d286
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first test
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2023-07-28 15:38:46 +08:00 |
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Ruige
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85fe9175e6
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backplaneslv compile pass
Signed-off-by: Ruige <295054118@whut.edu.cn>
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2023-07-25 21:05:43 +08:00 |
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