FSMC

src/main/scala/backBoard/BackBoardMst.scala

@@ -24,29 +24,5 @@ class BackBoardMst extends Module{
   val io: BackBoardMstIO = IO(new BackBoardMstIO)
 
 
-    val spi = Module( new SpiSlv )
-    val in  = Module( new CDR4MultiIn )
-    val out = Module( new CDROutBus )
-
-    spi.io.CS   := io.CS
-    io.MISO     := spi.io.MISO
-    spi.io.MOSI := io.MOSI
-    spi.io.SCK := io.SCK
-
-    // io.interrupt := spi.io.interrupt
-    io.interrupt := false.B
-
-    spi.io.CDRIn  <> in.io.latDat
-    spi.io.CDROut <> out.io.pkgDat
-
-    in.io.clk4 := io.clk4
-    spi.io.clk4 := io.clk4
-
-    in.io.dat  := io.downStreamReqDat
-    io.downStreamRespdat := out.io.dat
-
   
 }
-
-
-

src/main/scala/backBoard/FSMC.scala

@@ -0,0 +1,83 @@
+package BACK
+
+import chisel3._
+import chisel3.util._
+
+
+class FSMC_Port_Bundle extends Bundle{
+  // val clk = Input(Bool())
+  val addr    = Input(UInt(2.W))
+  val dataIn  = Input(UInt(8.W))
+  val dataOut = Output(UInt(8.W))
+  val dataOEn = Output(Bool())
+  val cen     = Input(Bool())
+  val oen     = Input(Bool())
+  val wen     = Input(Bool())
+}
+
+// class FSMC_Status_Bundle extends Bundle{
+//   val op      = UInt(2.W)
+//   val isBusy  = Bool()
+//   val isError = Bool()
+// }
+
+
+class FSMCSlvIO extends Bundle{
+  val FSMC = new FSMC_Port_Bundle
+
+  val CDRIn  = Flipped(Valid(new CDRData))
+  val CDROut = Valid(new CDRData)
+}
+
+class FSMCSlv extends Module{
+  val io: FSMCSlvIO = IO(new FSMCSlvIO)
+
+  val fsmcAddrSync   = ShiftRegister( io.FSMC.addr,   2, 0.U, true.B )
+  val fsmcdataInSync = ShiftRegister( io.FSMC.dataIn, 2, 0.U, true.B )
+  val fsmcCEnSync    = ShiftRegister( io.FSMC.cen,    2, true.B, true.B )
+  val fsmcOEnSync    = ShiftRegister( io.FSMC.oen,    2, true.B, true.B )
+  val fsmcWEnSync    = ShiftRegister( io.FSMC.wen,    2, true.B, true.B )
+
+  io.FSMC.dataOEn := io.FSMC.oen
+
+
+
+  val status  = RegInit(0.U(8.W))
+  val address = Reg(UInt(8.W))
+  val data    = Reg(UInt(8.W))
+  val none    = Reg(UInt(8.W))
+
+  val dataOutReg = RegInit(0.U(8.W)); io.FSMC.dataOut := dataOutReg
+
+
+
+  when( ~fsmcCEnSync & ~fsmcOEnSync ){
+    dataOutReg := 
+      Mux1H(Seq(
+        (fsmcAddrSync === 0.U) -> status,
+        (fsmcAddrSync === 1.U) -> address,
+        (fsmcAddrSync === 2.U) -> data,
+        (fsmcAddrSync === 3.U) -> none,
+      ))
+  } .elsewhen( ~fsmcCEnSync & ~fsmcWEnSync ){
+    when( fsmcAddrSync === 0.U ){
+      status := fsmcdataInSync
+    }
+    when( fsmcAddrSync === 1.U ){
+      address := fsmcdataInSync
+    }
+    when( fsmcAddrSync === 2.U ){
+      data := fsmcdataInSync
+    }
+    when( fsmcAddrSync === 3.U ){
+      none := fsmcdataInSync
+    }
+  }
+
+  when( io.CDRIn.fire ){
+    
+  }
+   
+
+}
+

src/main/scala/backBoard/trush/BackBoardMst.scala.bk

@@ -0,0 +1,52 @@
+package BACK
+
+import chisel3._
+import chisel3.util._
+
+
+class BackBoardMstIO extends Bundle{
+  val downStreamReqDat  = Input( Bool() )
+  val downStreamRespdat = Output(Bool())
+
+  val CS   = Input(Bool())
+  val MISO = Output(Bool())
+  val MOSI = Input(Bool())
+  val SCK  = Input(Bool())
+
+  val interrupt = Output(Bool())
+
+  val clk4            = Input( Bool() )
+
+}
+
+
+class BackBoardMst extends Module{
+  val io: BackBoardMstIO = IO(new BackBoardMstIO)
+
+
+    val spi = Module( new SpiSlv )
+    val in  = Module( new CDR4MultiIn )
+    val out = Module( new CDROutBus )
+
+    spi.io.CS   := io.CS
+    io.MISO     := spi.io.MISO
+    spi.io.MOSI := io.MOSI
+    spi.io.SCK := io.SCK
+
+    // io.interrupt := spi.io.interrupt
+    io.interrupt := false.B
+
+    spi.io.CDRIn  <> in.io.latDat
+    spi.io.CDROut <> out.io.pkgDat
+
+    in.io.clk4 := io.clk4
+    spi.io.clk4 := io.clk4
+
+    in.io.dat  := io.downStreamReqDat
+    io.downStreamRespdat := out.io.dat
+
+
+}
+
+
+