84 lines
1.9 KiB
Scala
84 lines
1.9 KiB
Scala
package BACK
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import chisel3._
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import chisel3.util._
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class FSMC_Port_Bundle extends Bundle{
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// val clk = Input(Bool())
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val addr = Input(UInt(2.W))
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val dataIn = Input(UInt(8.W))
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val dataOut = Output(UInt(8.W))
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val dataOEn = Output(Bool())
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val cen = Input(Bool())
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val oen = Input(Bool())
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val wen = Input(Bool())
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}
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// class FSMC_Status_Bundle extends Bundle{
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// val op = UInt(2.W)
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// val isBusy = Bool()
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// val isError = Bool()
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// }
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class FSMCSlvIO extends Bundle{
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val FSMC = new FSMC_Port_Bundle
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val CDRIn = Flipped(Valid(new CDRData))
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val CDROut = Valid(new CDRData)
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}
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class FSMCSlv extends Module{
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val io: FSMCSlvIO = IO(new FSMCSlvIO)
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val fsmcAddrSync = ShiftRegister( io.FSMC.addr, 2, 0.U, true.B )
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val fsmcdataInSync = ShiftRegister( io.FSMC.dataIn, 2, 0.U, true.B )
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val fsmcCEnSync = ShiftRegister( io.FSMC.cen, 2, true.B, true.B )
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val fsmcOEnSync = ShiftRegister( io.FSMC.oen, 2, true.B, true.B )
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val fsmcWEnSync = ShiftRegister( io.FSMC.wen, 2, true.B, true.B )
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io.FSMC.dataOEn := io.FSMC.oen
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val status = RegInit(0.U(8.W))
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val address = Reg(UInt(8.W))
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val data = Reg(UInt(8.W))
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val none = Reg(UInt(8.W))
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val dataOutReg = RegInit(0.U(8.W)); io.FSMC.dataOut := dataOutReg
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when( ~fsmcCEnSync & ~fsmcOEnSync ){
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dataOutReg :=
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Mux1H(Seq(
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(fsmcAddrSync === 0.U) -> status,
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(fsmcAddrSync === 1.U) -> address,
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(fsmcAddrSync === 2.U) -> data,
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(fsmcAddrSync === 3.U) -> none,
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))
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} .elsewhen( ~fsmcCEnSync & ~fsmcWEnSync ){
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when( fsmcAddrSync === 0.U ){
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status := fsmcdataInSync
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}
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when( fsmcAddrSync === 1.U ){
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address := fsmcdataInSync
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}
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when( fsmcAddrSync === 2.U ){
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data := fsmcdataInSync
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}
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when( fsmcAddrSync === 3.U ){
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none := fsmcdataInSync
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}
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}
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when( io.CDRIn.fire ){
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}
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}
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