From 6c2f0b02f81bb599b2fba752cecf19baf5ac133e Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Tue, 15 Aug 2023 08:42:56 +0000 Subject: [PATCH] FSMC --- src/main/scala/backBoard/BackBoardMst.scala | 28 +------ src/main/scala/backBoard/FSMC.scala | 83 +++++++++++++++++++ .../backBoard/trush/BackBoardMst.scala.bk | 52 ++++++++++++ .../BackBoardSlv.scala.bk} | 0 .../CDR4MultiIn.scala.bk} | 0 .../CDROutBus.scala.bk} | 0 .../{SpiSlv.scala => trush/SpiSlv.scala.bk} | 0 7 files changed, 137 insertions(+), 26 deletions(-) create mode 100644 src/main/scala/backBoard/FSMC.scala create mode 100644 src/main/scala/backBoard/trush/BackBoardMst.scala.bk rename src/main/scala/backBoard/{BackBoardSlv.scala => trush/BackBoardSlv.scala.bk} (100%) rename src/main/scala/backBoard/{CDR4MultiIn.scala => trush/CDR4MultiIn.scala.bk} (100%) rename src/main/scala/backBoard/{CDROutBus.scala => trush/CDROutBus.scala.bk} (100%) rename src/main/scala/backBoard/{SpiSlv.scala => trush/SpiSlv.scala.bk} (100%) diff --git a/src/main/scala/backBoard/BackBoardMst.scala b/src/main/scala/backBoard/BackBoardMst.scala index e3f623d..0cd2e14 100644 --- a/src/main/scala/backBoard/BackBoardMst.scala +++ b/src/main/scala/backBoard/BackBoardMst.scala @@ -24,29 +24,5 @@ class BackBoardMst extends Module{ val io: BackBoardMstIO = IO(new BackBoardMstIO) - val spi = Module( new SpiSlv ) - val in = Module( new CDR4MultiIn ) - val out = Module( new CDROutBus ) - - spi.io.CS := io.CS - io.MISO := spi.io.MISO - spi.io.MOSI := io.MOSI - spi.io.SCK := io.SCK - - // io.interrupt := spi.io.interrupt - io.interrupt := false.B - - spi.io.CDRIn <> in.io.latDat - spi.io.CDROut <> out.io.pkgDat - - in.io.clk4 := io.clk4 - spi.io.clk4 := io.clk4 - - in.io.dat := io.downStreamReqDat - io.downStreamRespdat := out.io.dat - - -} - - - + +} \ No newline at end of file diff --git a/src/main/scala/backBoard/FSMC.scala b/src/main/scala/backBoard/FSMC.scala new file mode 100644 index 0000000..bb6fa74 --- /dev/null +++ b/src/main/scala/backBoard/FSMC.scala @@ -0,0 +1,83 @@ +package BACK + +import chisel3._ +import chisel3.util._ + + +class FSMC_Port_Bundle extends Bundle{ + // val clk = Input(Bool()) + val addr = Input(UInt(2.W)) + val dataIn = Input(UInt(8.W)) + val dataOut = Output(UInt(8.W)) + val dataOEn = Output(Bool()) + val cen = Input(Bool()) + val oen = Input(Bool()) + val wen = Input(Bool()) +} + +// class FSMC_Status_Bundle extends Bundle{ +// val op = UInt(2.W) +// val isBusy = Bool() +// val isError = Bool() +// } + + +class FSMCSlvIO extends Bundle{ + val FSMC = new FSMC_Port_Bundle + + val CDRIn = Flipped(Valid(new CDRData)) + val CDROut = Valid(new CDRData) +} + +class FSMCSlv extends Module{ + val io: FSMCSlvIO = IO(new FSMCSlvIO) + + val fsmcAddrSync = ShiftRegister( io.FSMC.addr, 2, 0.U, true.B ) + val fsmcdataInSync = ShiftRegister( io.FSMC.dataIn, 2, 0.U, true.B ) + val fsmcCEnSync = ShiftRegister( io.FSMC.cen, 2, true.B, true.B ) + val fsmcOEnSync = ShiftRegister( io.FSMC.oen, 2, true.B, true.B ) + val fsmcWEnSync = ShiftRegister( io.FSMC.wen, 2, true.B, true.B ) + + io.FSMC.dataOEn := io.FSMC.oen + + + + val status = RegInit(0.U(8.W)) + val address = Reg(UInt(8.W)) + val data = Reg(UInt(8.W)) + val none = Reg(UInt(8.W)) + + val dataOutReg = RegInit(0.U(8.W)); io.FSMC.dataOut := dataOutReg + + + + when( ~fsmcCEnSync & ~fsmcOEnSync ){ + dataOutReg := + Mux1H(Seq( + (fsmcAddrSync === 0.U) -> status, + (fsmcAddrSync === 1.U) -> address, + (fsmcAddrSync === 2.U) -> data, + (fsmcAddrSync === 3.U) -> none, + )) + } .elsewhen( ~fsmcCEnSync & ~fsmcWEnSync ){ + when( fsmcAddrSync === 0.U ){ + status := fsmcdataInSync + } + when( fsmcAddrSync === 1.U ){ + address := fsmcdataInSync + } + when( fsmcAddrSync === 2.U ){ + data := fsmcdataInSync + } + when( fsmcAddrSync === 3.U ){ + none := fsmcdataInSync + } + } + + when( io.CDRIn.fire ){ + + } + + +} + diff --git a/src/main/scala/backBoard/trush/BackBoardMst.scala.bk b/src/main/scala/backBoard/trush/BackBoardMst.scala.bk new file mode 100644 index 0000000..e3f623d --- /dev/null +++ b/src/main/scala/backBoard/trush/BackBoardMst.scala.bk @@ -0,0 +1,52 @@ +package BACK + +import chisel3._ +import chisel3.util._ + + +class BackBoardMstIO extends Bundle{ + val downStreamReqDat = Input( Bool() ) + val downStreamRespdat = Output(Bool()) + + val CS = Input(Bool()) + val MISO = Output(Bool()) + val MOSI = Input(Bool()) + val SCK = Input(Bool()) + + val interrupt = Output(Bool()) + + val clk4 = Input( Bool() ) + +} + + +class BackBoardMst extends Module{ + val io: BackBoardMstIO = IO(new BackBoardMstIO) + + + val spi = Module( new SpiSlv ) + val in = Module( new CDR4MultiIn ) + val out = Module( new CDROutBus ) + + spi.io.CS := io.CS + io.MISO := spi.io.MISO + spi.io.MOSI := io.MOSI + spi.io.SCK := io.SCK + + // io.interrupt := spi.io.interrupt + io.interrupt := false.B + + spi.io.CDRIn <> in.io.latDat + spi.io.CDROut <> out.io.pkgDat + + in.io.clk4 := io.clk4 + spi.io.clk4 := io.clk4 + + in.io.dat := io.downStreamReqDat + io.downStreamRespdat := out.io.dat + + +} + + + diff --git a/src/main/scala/backBoard/BackBoardSlv.scala b/src/main/scala/backBoard/trush/BackBoardSlv.scala.bk similarity index 100% rename from src/main/scala/backBoard/BackBoardSlv.scala rename to src/main/scala/backBoard/trush/BackBoardSlv.scala.bk diff --git a/src/main/scala/backBoard/CDR4MultiIn.scala b/src/main/scala/backBoard/trush/CDR4MultiIn.scala.bk similarity index 100% rename from src/main/scala/backBoard/CDR4MultiIn.scala rename to src/main/scala/backBoard/trush/CDR4MultiIn.scala.bk diff --git a/src/main/scala/backBoard/CDROutBus.scala b/src/main/scala/backBoard/trush/CDROutBus.scala.bk similarity index 100% rename from src/main/scala/backBoard/CDROutBus.scala rename to src/main/scala/backBoard/trush/CDROutBus.scala.bk diff --git a/src/main/scala/backBoard/SpiSlv.scala b/src/main/scala/backBoard/trush/SpiSlv.scala.bk similarity index 100% rename from src/main/scala/backBoard/SpiSlv.scala rename to src/main/scala/backBoard/trush/SpiSlv.scala.bk