66 lines
1.3 KiB
Plaintext
66 lines
1.3 KiB
Plaintext
package BACK
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import chisel3._
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import chisel3.util._
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class CDROutBusIO() extends Bundle{
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val pkgDat = Flipped(Decoupled(new CDRData))
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val dat = Output(Bool())
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}
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class CDROutBus extends Module{
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val io: CDROutBusIO = IO(new CDROutBusIO)
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val isBusy = RegInit(false.B)
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io.pkgDat.ready := ~isBusy
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val address = Reg(UInt(6.W))
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val register = Reg(UInt(8.W))
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val data = Reg(UInt(32.W))
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val hash = Reg(UInt(16.W))
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val cnt = RegInit( 0.U(7.W) )
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when( cnt === (1+6+8+32+16).U ){
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isBusy := false.B
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} .elsewhen( io.pkgDat.fire ){
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isBusy := true.B
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address := io.pkgDat.bits.address
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register := io.pkgDat.bits.register
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data := io.pkgDat.bits.data
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}
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when(io.pkgDat.fire){
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cnt := 0.U
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} .elsewhen( isBusy ){
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cnt := cnt + 1.U
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}
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when( cnt === 1.U ){
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io.dat := true.B
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} .elsewhen( cnt >= (1 + 1).U && cnt < (6 + 1 + 1).U ){
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io.dat := address(5)
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address := address << 1
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} .elsewhen( cnt >= (1 + 1 + 6).U && cnt < (8 + 1+ 1 + 6).U ){
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io.dat := register(7)
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register := register << 1
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} .elsewhen( cnt >= (1 + 1 + 6 + 8).U && cnt < (32 + 1 + 1 + 6 + 8).U ){
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io.dat := data(31)
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data := data << 1
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} .elsewhen( cnt >= (1 + 1 + 6 + 8 + 32).U && cnt < (16 + 1 + 1 + 6 + 8 + 32).U ){
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io.dat := hash(15)
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hash := hash << 1
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} .otherwise{
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io.dat := false.B
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}
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}
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