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eb001/tb/sw/src/slvStartup.S

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740 B
ArmAsm
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#include "custom_ops.S"
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.extern main
.globl _prog_start
.section .text.init
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_prog_start:
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li sp, 0
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picorv32_maskirq_insn(zero, zero)
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call main
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ecall
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.balign 32
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.section .trap_entry, "ax", %progbits
trap_entry:
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# q0 return address
# q1 bitmask of all IRQ to be handled, may be more than one IRQ
# q2 q3 unused, can be use as temp storage register
# q Without the q-registers, the irq return address will be stored in x3 (gp) and the IRQ bitmask in x4 (tp),
# io.interrupt(0) := intTxError
# io.interrupt(1) := intRxError
# io.interrupt(2) := intRxStart
# io.interrupt(3) := intRxEnd
or sp, sp, x4
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andi x4, x4, 0x2
beqz x4, 1f
li x4, 0
sw x3, 0x400(x0)
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1:
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picorv32_retirq_insn()