ruige/eb001
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

下行转发测试通过，差一个last设备启动上行

Browse Source
This commit is contained in:
RuigeLee
2024-10-30 17:11:59 +08:00
parent 498fa92a80
commit 430bb94381
5 changed files with 59 additions and 92 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
Makefile
View File

@@ -87,7 +87,7 @@ sw:
riscv64-unknown-elf-gcc -Os -ggdb -march=rv32i -mabi=ilp32 -Wall -mcmodel=medany -mexplicit-relocs \
riscv64-unknown-elf-gcc -O3 -ggdb -march=rv32i -mabi=ilp32 -Wall -mcmodel=medany -mexplicit-relocs \
-I ./tb/sw/ -I ./tb/sw/src \
-c ./tb/sw/src/slvMain.c \
-o ./tb/sw/build/slvMain.o

1
src/main/scala/backBoard/pico/TLCDR.scala
View File

@@ -205,7 +205,6 @@ class TLCDR(edge: TLEdgeIn)(implicit p: Parameters) extends TLCDRBase(edge) with
io.interrupt(0) := intTxError
io.interrupt(1) := intRxError
io.interrupt(2) := intRxStart
io.interrupt(3) := intRxEnd

2
tb/backSys_tb.v
View File

@@ -104,7 +104,7 @@ initial begin
reset <= 0;
# 10000000
# 1000000
$display("Time Out !!!");
$stop;
end

113
tb/sw/src/SlvMain.c
View File

@@ -48,20 +48,14 @@ void main()
asm volatile (
"1:\n"
"beqz sp, 1b\n"
"li ra, 1\n"
"sub sp, sp, ra\n"
"andi ra, sp, 0x04\n"
"beqz ra, 1b\n"
"andi sp, sp, 0xFB\n"
);
readDat = *cdr_0_rx_rxFifo;
operator = (readDat >> 16) & 0xf;
downRecvLen = readDat >> 24;
asm volatile (
"1:\n"
"beqz sp, 1b\n"
"addi sp, sp, -1\n"
);
downRecvLen = readDat >> 20;
readDat = *cdr_0_rx_rxFifo;
@@ -73,48 +67,51 @@ void main()
//接收本地包
for( uint8_t i = 0; i < 8/4; i++ ){
asm volatile (
"1:\n"
"beqz sp, 1b\n"
"addi sp, sp, -1\n"
);
asm volatile (
"andi ra, sp, 0x08\n"
"1:\n"
"bnez ra, 1b\n" //error
);
readDat = *cdr_0_rx_rxFifo;
}
// 下行包头
*cdr_0_tx_txLen = downRecvLen; //downSendLen + 8
*cdr_0_tx_txFifo = (downSendLen << 24) |( 0 << 16) | 0;
*cdr_0_tx_txFifo = (downSendLen << 20) |( 0 << 16) | 0;
*cdr_0_tx_txFifo = 0;
//下行负载
for( uint16_t i = 0; i < (downSendLen >> 3); i++ ){ //一次传4byte
asm volatile (
"1:\n"
"beqz sp, 1b\n"
"addi sp, sp, -1\n"
);
*cdr_0_tx_txFifo = *cdr_0_rx_rxFifo; //接收即发送
asm volatile (
"lui t0, %hi(0x40000000)\n"
);
for( uint32_t i = 0; i < (downSendLen >> 2); i++ ){ //一次传4byte
asm volatile (
// "andi ra, sp, 0x08\n"
// "1:\n"
// "bnez ra, 1b\n" //error 速度不够，不再检查接收
// "lui t0, %hi(0x40000000)\n"
"lw t1, 0x1c(t0)\n"
"sw t1, 0x08(t0)\n"
// : : : "a0", "a1"
);
//*cdr_0_tx_txFifo = *cdr_0_rx_rxFifo; //接收即发送
}
//CRC
asm volatile (
"andi ra, sp, 0x08\n"
"1:\n"
"beqz sp, 1b\n"
"addi sp, sp, -1\n"
"bnez ra, 1b\n" //error
);
uint32_t crc = *cdr_0_rx_rxFifo; //CRC
asm volatile ( //等待发送完成标志
"1:\n"
"andi ra, x4, 0x4\n"
"beqz x4, 1b\n"
);
//等待接收完成标志
asm volatile (
"beqz sp, 2f\n"
"1:"
"j 1b\n"
"2:\n"
"1:\n"
"andi ra, sp, 0x08\n"
"beqz ra, 1b\n"
"andi sp, sp, 0xF7\n"
);
@@ -123,48 +120,38 @@ void main()
//接收第一个包
asm volatile (
"1:\n"
"beqz sp, 1b\n"
"addi sp, sp, -1\n"
"andi ra, sp, 0x40\n"
"beqz ra, 1b\n"
"andi sp, sp, 0xBF\n"
);
readDat = *cdr_1_rx_rxFifo;
operator = (readDat >> 16) & 0xf;
upRecvLen = readDat >> 24;
upRecvLen = readDat >> 20;
totNum = slvNum + (upRecvLen >> 3) - 1;
//接收第二个包
asm volatile (
"1:\n"
"beqz sp, 1b\n"
"addi sp, sp, -1\n"
"andi ra, sp, 0x80\n"
"1:\n"
"bnez ra, 1b\n" //error
);
readDat = *cdr_1_rx_rxFifo;
//发送上行包头
*cdr_1_tx_txLen = upRecvLen + 16; //downSendLen + 8
*cdr_1_tx_txFifo = ((upRecvLen + 8) << 24) |( 0 << 16) | 0;
*cdr_1_tx_txFifo = ((upRecvLen + 8) << 20) |( 0 << 16) | 0;
*cdr_1_tx_txFifo = 0;
for( uint8_t i = 0; i < 8/4; i ++ ){
*cdr_1_tx_txFifo = 0;
}
for( uint16_t i = 0; i < upRecvLen >> 3; i ++ ){ //一次传4byte
for( uint16_t i = 0; i < upRecvLen >> 2; i ++ ){ //一次传4byte
asm volatile (
"andi ra, sp, 0x80\n"
"1:\n"
"andi ra, x4, 0x40\n"
"beqz ra, 3f\n"
"2:\n"
"lui ra, %hi(0x40000000)\n"
"lw ra, 0x80(ra)\n"
"andi ra, ra, 0x20\n"
"bnez ra, 2b\n"
"3:\n"
"beqz sp, 1b\n"
"addi sp, sp, -1\n"
"bnez ra, 1b\n" //error
);
*cdr_1_tx_txFifo = *cdr_1_rx_rxFifo; //接收即发送
@@ -172,16 +159,18 @@ void main()
//CRC
asm volatile (
"andi ra, sp, 0x80\n"
"1:\n"
"beqz sp, 1b\n"
"addi sp, sp, -1\n"
"bnez ra, 1b\n" //error
);
crc = *cdr_1_rx_rxFifo; //CRC
//等待接收完成标志
asm volatile (
"beqz sp, 2f\n"
"1:"
"j 1b\n"
"2:\n"
"1:\n"
"andi ra, sp, 0x80\n"
"beqz ra, 1b\n"
"andi sp, sp, 0x7F\n"
);
} else if ( operator == 1 ){

33
tb/sw/src/slvStartup.S
View File

@@ -27,36 +27,15 @@ trap_entry:
# q寄存器已经禁用， Without the q-registers, the irq return address will be stored in x3 (gp) and the IRQ bitmask in x4 (tp),
# addi x15, x4, 0
# io.interrupt(0) := intTxError
# io.interrupt(1) := intRxError
# io.interrupt(2) := intRxStart
# io.interrupt(3) := intRxEnd
# io.interrupt(0) := intTxError
# io.interrupt(1) := intTxFifoFull
# io.interrupt(2) := intTxFinish
# io.interrupt(3) := intRxError
# io.interrupt(4) := intRxValid
# io.interrupt(5) := intTxError
# io.interrupt(6) := intTxFifoFull
# io.interrupt(7) := intTxFinish
or sp, sp, x4
# io.interrupt(8) := intRxError
# io.interrupt(9) := intRxValid
# andi ra, x4, 0x02
# bnez ra, 1f
# addi, sp, sp, 2048
1:
andi ra, x4, 0x10
bnez ra, 2f
addi sp, sp, 1
2:
# andi ra, x4, 0x40
# bnez ra, 3f
# addi, sp, sp, 2048
3:
andi ra, x4, 0x200
bnez ra, 4f
addi sp, sp, 1
4:
picorv32_retirq_insn()