2024-11-04 16:07:06 +08:00
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#include <stdint.h>
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2025-01-15 11:44:30 +08:00
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#include "tl2cdr.h"
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2025-02-09 01:17:17 +08:00
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#include "mstMainCfg.h"
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#include "sysDef.h"
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2024-11-04 16:07:06 +08:00
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2025-02-10 00:03:16 +08:00
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volatile uint32_t *const plic_priority = (uint32_t *)(0xc000000U);
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2025-01-15 17:58:12 +08:00
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2025-01-15 15:44:29 +08:00
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volatile uint32_t *plic_pending_0_31 = (uint32_t*)( 0xc000000U + 0X001000 );
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volatile uint32_t *plic_enable_0_31 = (uint32_t*)( 0xc000000U + 0X002000 );
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2025-01-15 17:58:12 +08:00
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volatile uint32_t *plic_threshold_0 = (uint32_t*)( 0xc000000U + 0X200000 );
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2025-01-15 15:44:29 +08:00
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volatile uint32_t *plic_claim = (uint32_t*)( 0xc000000U + 0X200004 );
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2025-02-09 01:17:17 +08:00
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uint8_t MST_TX_BUF[TX_BUF_NUM * TX_BUF_MAX_LEN] __attribute__((aligned(32)));
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uint8_t MST_RX_BUF[RX_BUF_NUM * RX_BUF_MAX_LEN] __attribute__((aligned(32)));
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2024-11-04 16:07:06 +08:00
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static inline void error() {
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while(1);
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}
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2025-02-09 01:17:17 +08:00
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extern const uint8_t int_svr_code[];
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uint32_t (*sys_call)(uint32_t no, ...);
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2024-11-04 16:07:06 +08:00
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void main()
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{
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2025-02-09 01:17:17 +08:00
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int i;
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/*初始化plic*/
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*plic_enable_0_31 = 1 << CDR_INT_TX0END
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//| 1 << CDR_INT_TX1END
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//| 1 << CDR_INT_RX0ERROR
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| 1 << CDR_INT_RX1ERROR
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//| 1 << CDR_INT_RX0START
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| 1 << CDR_INT_RX1START
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//| 1 << CDR_INT_RX0END
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| 1 << CDR_INT_RX1END
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| 1 << CDR_INT_TX0_FIFO_DEQ
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//| 1 << CDR_INT_TX1_FIFO_DEQ
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//| 1 << CDR_INT_RX0_FIFO_ENQ
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| 1 << CDR_INT_RX1_FIFO_ENQ
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;
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2025-02-10 00:03:16 +08:00
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plic_priority[CDR_INT_TX0END] = 1;
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plic_priority[CDR_INT_TX1END] = 1;
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plic_priority[CDR_INT_RX0ERROR] = 1;
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plic_priority[CDR_INT_RX1ERROR] = 1;
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plic_priority[CDR_INT_RX0START] = 1;
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plic_priority[CDR_INT_RX1START] = 1;
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plic_priority[CDR_INT_RX0END] = 1;
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plic_priority[CDR_INT_RX1END] = 1;
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plic_priority[CDR_INT_TX0_FIFO_DEQ] = 1;
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plic_priority[CDR_INT_TX1_FIFO_DEQ] = 1;
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plic_priority[CDR_INT_RX0_FIFO_ENQ] = 1;
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plic_priority[CDR_INT_RX1_FIFO_ENQ] = 1;
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2025-01-15 17:58:12 +08:00
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*plic_threshold_0 = 0;
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2025-01-15 15:44:29 +08:00
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2025-02-09 01:17:17 +08:00
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#if 0
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//再写一次实现延迟,等从机的复位完成
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*plic_enable_0_31 = 1 << CDR_INT_TXEND | 1 << CDR_INT_RXERROR | 1 << CDR_INT_RXSTART | 1 << CDR_INT_RXEND;
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*plic_priority_TxEnd = 1;
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*plic_priority_RxError = 1;
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*plic_priority_RxStart = 1;
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*plic_priority_RxEnd = 1;
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*plic_threshold_0 = 0;
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#else
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//延迟等待从机复位,初始化
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for (i = 0; i < 100; i++)
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asm volatile("nop");
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2025-02-10 00:03:16 +08:00
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2025-02-09 01:17:17 +08:00
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#endif
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2025-01-17 16:21:46 +08:00
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2025-02-03 07:51:54 +08:00
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//while (init_svr_code() != 1);
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2025-02-09 01:17:17 +08:00
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sys_call = (void *)int_svr_code;
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2025-01-17 16:21:46 +08:00
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2024-11-04 16:07:06 +08:00
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2025-02-09 01:17:17 +08:00
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//复位脉冲
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*tx0_softReset = 1;
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*tx1_softReset = 1;
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*rx0_softReset = 1;
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*rx1_softReset = 1;
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2025-01-15 15:44:29 +08:00
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2024-11-04 16:07:06 +08:00
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2025-02-09 01:17:17 +08:00
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//tx0 下行
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//tx1 上行
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//rx0 下行
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//rx1 上行
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uint32_t tx_len;
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tx_len = 32;
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2025-02-09 20:08:14 +08:00
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for (i = 0; i < tx_len - 1; i++)
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2025-02-09 01:17:17 +08:00
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{
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MST_TX_BUF[i] = i;
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}
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2024-11-04 16:07:06 +08:00
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2025-02-09 01:17:17 +08:00
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sys_call(SYS_SET_RECV_INFO, MST_RX_BUF);
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sys_call(SYS_SEND_DATA, MST_TX_BUF, tx_len);
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2024-11-05 11:09:40 +08:00
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2025-02-09 01:17:17 +08:00
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while (1);
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#if 0
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*cdr_txLen = 520; //总长520
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*cdr_txFifo = (512 << 20) |( 0 << 16) | 0x0000; //负载长度512,操作数0, 参数全0
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*cdr_txFifo = 0x00000000;
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2024-11-04 16:07:06 +08:00
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2025-02-03 23:49:50 +08:00
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for( uint32_t i = 0; i < 512/4 - 1; i ++ ){
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2025-01-15 11:44:30 +08:00
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*cdr_txFifo = 0x00000000;
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2024-11-04 16:07:06 +08:00
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}
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2025-02-03 23:49:50 +08:00
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crc = *cdr_txCrc;
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*cdr_txFifo = crc;
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2024-11-04 16:07:06 +08:00
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//等待发送完成标志
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2025-01-15 15:44:29 +08:00
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// asm volatile (
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// "1:\n"
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// "andi %0, sp, 0x01\n"
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// "beqz %0, 1b\n"
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// "andi sp, sp, 0xFE\n"
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// :"+r"(flag)
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// );
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while( !flag_intTxEnd );
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flag_intTxEnd = 0;
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2024-11-04 16:07:06 +08:00
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*cdr_softReset = 1; //复位脉冲
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*cdr_direct = 1; //方向切换上行
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//接收第一个包
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2025-01-15 15:44:29 +08:00
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// asm volatile (
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// "1:\n"
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// "andi %0, sp, 0x04\n"
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// "beqz %0, 1b\n"
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// "andi sp, sp, 0xFB\n"
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// :"+r"(flag)
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// );
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while(!flag_intRxStart);
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flag_intRxStart = 0;
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2024-11-04 16:07:06 +08:00
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readDat = *cdr_rxFifo;
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// operator = (readDat >> 16) & 0xf; //速度不够,不校验
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upRecvLen = readDat >> 20;
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//接收第二个包
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2025-01-15 15:44:29 +08:00
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// asm volatile (
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// "andi %0, sp, 0x08\n"
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// "1:\n"
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// "bnez %0, 1b\n" //error //速度不够,不校验
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// :"+r"(flag),
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// );
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if( flag_intRxError ){
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while(1);
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}
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2024-11-04 16:07:06 +08:00
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uint32_t temp = *cdr_rxFifo;
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//上行转发负载
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for( uint32_t i = 0; i < (upRecvLen >> 2); i ++ ){ //一次传4byte
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2025-01-15 15:44:29 +08:00
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if( flag_intRxError ){
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while(1);
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}
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// register uint32_t upData;
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// asm volatile (
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// "andi %0, sp, 0x80\n"
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// "1:\n"
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// "bnez %0, 1b\n" //error 速度不够,不再检查接收
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// "lw %1, 0x01c(x0)\n"
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// :"+r"(flag), "+r"(upData)
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// );
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2024-11-04 16:07:06 +08:00
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}
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//CRC
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2025-01-15 15:44:29 +08:00
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if( flag_intRxError ){
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while(1);
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}
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// asm volatile (
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// "andi %0, sp, 0x08\n"
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// "1:\n"
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// "bnez %0, 1b\n" //error
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// :"+r"(flag)
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// );
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2025-02-03 23:49:50 +08:00
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//uint32_t crc = *cdr_rxFifo; //CRC
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2024-11-04 16:07:06 +08:00
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//等待接收完成标志
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2025-01-15 15:44:29 +08:00
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// asm volatile (
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// "1:\n"
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// "andi %0, sp, 0x08\n"
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// "beqz %0, 1b\n"
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// "andi sp, sp, 0xF7\n"
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// :"+r"(flag)
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// );
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while(!flag_intRxEnd);
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flag_intRxEnd = 0;
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2024-11-04 16:07:06 +08:00
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totNum = (upRecvLen >> 3);
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2025-02-09 01:17:17 +08:00
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#endif
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2024-12-02 15:00:03 +08:00
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2024-11-04 16:07:06 +08:00
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}
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