2024-11-04 16:07:06 +08:00
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#include <stdint.h>
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// #include "uart.h"
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// #include "gpio.h"
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// #include "timer.h"
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2025-01-15 11:44:30 +08:00
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#include "tl2cdr.h"
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2024-11-04 16:07:06 +08:00
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2025-01-15 17:58:12 +08:00
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volatile uint32_t *plic_priority_3 = (uint32_t*)( 0xc000000U + 0X000004 * 3);
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volatile uint32_t *plic_priority_4 = (uint32_t*)( 0xc000000U + 0X000004 * 4);
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volatile uint32_t *plic_priority_5 = (uint32_t*)( 0xc000000U + 0X000004 * 5);
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volatile uint32_t *plic_priority_6 = (uint32_t*)( 0xc000000U + 0X000004 * 6);
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2025-01-27 22:25:39 +08:00
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volatile uint32_t *plic_priority_TxEnd = (uint32_t*)( 0xc000000U + 0X000004 * CDR_INT_TXEND);
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volatile uint32_t *plic_priority_RxError = (uint32_t*)( 0xc000000U + 0X000004 * CDR_INT_RXERROR);
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volatile uint32_t *plic_priority_RxStart = (uint32_t*)( 0xc000000U + 0X000004 * CDR_INT_RXSTART);
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volatile uint32_t *plic_priority_RxEnd = (uint32_t*)( 0xc000000U + 0X000004 * CDR_INT_RXEND);
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2025-01-22 17:12:40 +08:00
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volatile uint32_t *plic_priority_18 = (uint32_t*)( 0xc000000U + 0X000004 * 18);
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volatile uint32_t *plic_priority_19 = (uint32_t*)( 0xc000000U + 0X000004 * 19);
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volatile uint32_t *plic_priority_20 = (uint32_t*)( 0xc000000U + 0X000004 * 20);
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volatile uint32_t *plic_priority_21 = (uint32_t*)( 0xc000000U + 0X000004 * 21);
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2025-01-15 17:58:12 +08:00
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2025-01-15 15:44:29 +08:00
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volatile uint32_t *plic_pending_0_31 = (uint32_t*)( 0xc000000U + 0X001000 );
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volatile uint32_t *plic_enable_0_31 = (uint32_t*)( 0xc000000U + 0X002000 );
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2025-01-15 17:58:12 +08:00
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volatile uint32_t *plic_threshold_0 = (uint32_t*)( 0xc000000U + 0X200000 );
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2025-01-15 15:44:29 +08:00
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volatile uint32_t *plic_claim = (uint32_t*)( 0xc000000U + 0X200004 );
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2025-01-15 17:58:12 +08:00
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volatile uint32_t flag_intTxEnd = 0;
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volatile uint32_t flag_intRxError = 0;
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volatile uint32_t flag_intRxStart = 0;
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volatile uint32_t flag_intRxEnd = 0;
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2025-01-15 15:44:29 +08:00
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2025-01-15 17:58:12 +08:00
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void plic_handle(){
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2025-01-15 15:44:29 +08:00
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2025-01-15 17:58:12 +08:00
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// 从 PLIC 中获取中断源 ID
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uint32_t claim = *plic_claim;
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2025-01-27 22:25:39 +08:00
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if( claim == CDR_INT_TXEND ){
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2025-01-15 15:44:29 +08:00
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flag_intTxEnd = 1;
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2025-01-27 22:25:39 +08:00
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} else if( claim == CDR_INT_RXERROR ){
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2025-01-15 15:44:29 +08:00
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flag_intRxError = 1;
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2025-01-27 22:25:39 +08:00
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} else if( claim == CDR_INT_RXSTART ){
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2025-01-15 15:44:29 +08:00
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flag_intRxStart = 1;
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2025-01-27 22:25:39 +08:00
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} else if( claim == CDR_INT_RXEND ){
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2025-01-15 15:44:29 +08:00
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flag_intRxEnd = 1;
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}
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2025-01-15 17:58:12 +08:00
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// 通知 PLIC 完成中断处理
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*plic_claim = claim;
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2025-01-15 15:44:29 +08:00
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return;
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}
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2024-11-04 16:07:06 +08:00
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static inline void error() {
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while(1);
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}
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2025-01-15 11:44:30 +08:00
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// extern volatile uint32_t *cdr_status = (uint32_t*)( TL2CDR_BASE + CDR_ReadStatus ); //read
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// extern volatile uint32_t *cdr_txLen = (uint32_t*)( TL2CDR_BASE + CDR_WriteTxLen ); //write
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// extern volatile uint32_t *cdr_txFifo = (uint32_t*)( TL2CDR_BASE + CDR_WriteTxFifo ); //write
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// extern volatile uint32_t *cdr_direct = (uint32_t*)( TL2CDR_BASE + CDR_WriteTransDir ); //write
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// extern volatile uint32_t *cdr_softReset = (uint32_t*)( TL2CDR_BASE + CDR_WriteSoftReset ); //write
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// extern volatile uint32_t *cdr_rxLen = (uint32_t*)( TL2CDR_BASE + CDR_ReadRxLen ); //read
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// extern volatile uint32_t *cdr_rxFifo = (uint32_t*)( TL2CDR_BASE + CDR_ReadRxFifo ); //read
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2024-11-04 16:07:06 +08:00
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2025-02-03 07:51:54 +08:00
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//extern const uint8_t mst_svr_code[];
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//uint32_t (*init_svr_code)(void);
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2024-11-04 16:07:06 +08:00
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void main()
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{
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uint32_t readDat;
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uint32_t operator;
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uint32_t downRecvLen;
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uint32_t upRecvLen;
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uint32_t slvNum;
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uint32_t totNum;
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uint32_t isLast;
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2024-11-05 11:09:40 +08:00
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uint32_t led = 0;
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2025-02-03 23:49:50 +08:00
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uint32_t crc;
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2024-11-05 11:09:40 +08:00
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2025-02-03 07:51:54 +08:00
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//init_svr_code = (uint32_t (*)(void))mst_svr_code;
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2025-01-27 22:25:39 +08:00
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*plic_enable_0_31 = 1 << CDR_INT_TXEND | 1 << CDR_INT_RXERROR | 1 << CDR_INT_RXSTART | 1 << CDR_INT_RXEND;
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*plic_priority_TxEnd = 1;
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*plic_priority_RxError = 1;
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*plic_priority_RxStart = 1;
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*plic_priority_RxEnd = 1;
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2025-01-15 17:58:12 +08:00
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*plic_threshold_0 = 0;
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2025-01-15 15:44:29 +08:00
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2025-01-17 16:21:46 +08:00
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{//再写一次实现延迟,等从机的复位完成
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2025-01-27 22:25:39 +08:00
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*plic_enable_0_31 = 1 << CDR_INT_TXEND | 1 << CDR_INT_RXERROR | 1 << CDR_INT_RXSTART | 1 << CDR_INT_RXEND;
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*plic_priority_TxEnd = 1;
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*plic_priority_RxError = 1;
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*plic_priority_RxStart = 1;
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*plic_priority_RxEnd = 1;
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*plic_threshold_0 = 0;
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2025-01-17 16:21:46 +08:00
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}
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2025-02-03 07:51:54 +08:00
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//while (init_svr_code() != 1);
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2025-01-17 16:21:46 +08:00
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2024-11-04 16:07:06 +08:00
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2025-01-17 16:21:46 +08:00
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*cdr_softReset = 1; //复位脉冲
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*cdr_direct = 0;
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2025-01-15 15:44:29 +08:00
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2025-01-17 16:21:46 +08:00
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register uint32_t flag;
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2024-11-04 16:07:06 +08:00
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2025-01-15 17:58:12 +08:00
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// asm volatile ( //timer 2s
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// "1:\n"
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// "rdcycle %0\n"
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// // "srli %0, %0, 12\n"
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// "srli %0, %0, 27\n"
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// // "srli %0, %0, 26\n"
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// "andi %0, %0, 0x1\n"
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// "beqz %0, 1b\n"
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// :"+r"(flag)
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// );
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2024-11-04 16:07:06 +08:00
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2024-12-02 15:00:03 +08:00
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// if( led ){
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// *WriteGpio = 0xFFFFFFFF;
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// led = 0;
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// } else{
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// *WriteGpio = 0x0;
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// led = 1;
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// }
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2024-11-05 11:09:40 +08:00
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2024-11-04 16:07:06 +08:00
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//发送下行包头
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*cdr_txLen = 520; //总长520
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2025-01-15 11:44:30 +08:00
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*cdr_txFifo = (512 << 20) |( 0 << 16) | 0x0000; //负载长度512,操作数0, 参数全0
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*cdr_txFifo = 0x00000000;
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2024-11-04 16:07:06 +08:00
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2025-02-03 23:49:50 +08:00
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for( uint32_t i = 0; i < 512/4 - 1; i ++ ){
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2025-01-15 11:44:30 +08:00
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*cdr_txFifo = 0x00000000;
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2024-11-04 16:07:06 +08:00
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}
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2025-02-03 23:49:50 +08:00
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crc = *cdr_txCrc;
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*cdr_txFifo = crc;
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2024-11-04 16:07:06 +08:00
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//等待发送完成标志
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2025-01-15 15:44:29 +08:00
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// asm volatile (
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// "1:\n"
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// "andi %0, sp, 0x01\n"
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// "beqz %0, 1b\n"
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// "andi sp, sp, 0xFE\n"
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// :"+r"(flag)
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// );
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while( !flag_intTxEnd );
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flag_intTxEnd = 0;
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2024-11-04 16:07:06 +08:00
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*cdr_softReset = 1; //复位脉冲
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*cdr_direct = 1; //方向切换上行
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//接收第一个包
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2025-01-15 15:44:29 +08:00
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// asm volatile (
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// "1:\n"
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// "andi %0, sp, 0x04\n"
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// "beqz %0, 1b\n"
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// "andi sp, sp, 0xFB\n"
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// :"+r"(flag)
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// );
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while(!flag_intRxStart);
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flag_intRxStart = 0;
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2024-11-04 16:07:06 +08:00
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readDat = *cdr_rxFifo;
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// operator = (readDat >> 16) & 0xf; //速度不够,不校验
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upRecvLen = readDat >> 20;
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//接收第二个包
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2025-01-15 15:44:29 +08:00
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// asm volatile (
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// "andi %0, sp, 0x08\n"
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// "1:\n"
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// "bnez %0, 1b\n" //error //速度不够,不校验
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// :"+r"(flag),
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// );
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if( flag_intRxError ){
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while(1);
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}
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2024-11-04 16:07:06 +08:00
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uint32_t temp = *cdr_rxFifo;
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//上行转发负载
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for( uint32_t i = 0; i < (upRecvLen >> 2); i ++ ){ //一次传4byte
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2025-01-15 15:44:29 +08:00
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if( flag_intRxError ){
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while(1);
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}
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// register uint32_t upData;
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// asm volatile (
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// "andi %0, sp, 0x80\n"
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// "1:\n"
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// "bnez %0, 1b\n" //error 速度不够,不再检查接收
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// "lw %1, 0x01c(x0)\n"
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// :"+r"(flag), "+r"(upData)
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// );
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2024-11-04 16:07:06 +08:00
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}
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//CRC
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2025-01-15 15:44:29 +08:00
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if( flag_intRxError ){
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while(1);
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}
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// asm volatile (
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// "andi %0, sp, 0x08\n"
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// "1:\n"
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// "bnez %0, 1b\n" //error
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// :"+r"(flag)
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// );
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2025-02-03 23:49:50 +08:00
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//uint32_t crc = *cdr_rxFifo; //CRC
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2024-11-04 16:07:06 +08:00
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//等待接收完成标志
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2025-01-15 15:44:29 +08:00
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// asm volatile (
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// "1:\n"
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// "andi %0, sp, 0x08\n"
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// "beqz %0, 1b\n"
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// "andi sp, sp, 0xF7\n"
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// :"+r"(flag)
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// );
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while(!flag_intRxEnd);
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flag_intRxEnd = 0;
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2024-11-04 16:07:06 +08:00
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totNum = (upRecvLen >> 3);
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2024-12-02 15:00:03 +08:00
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2024-11-04 16:07:06 +08:00
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}
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