2024-10-29 17:32:17 +08:00
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#include <stdint.h>
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// #include "uart.h"
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// #include "gpio.h"
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// #include "timer.h"
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2025-01-16 16:34:48 +08:00
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#include "tl2cdr.h"
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2025-02-10 00:08:30 +08:00
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#include "system_cfg.h"
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2024-11-05 17:48:34 +08:00
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2025-01-27 22:25:39 +08:00
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2025-02-10 00:03:16 +08:00
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volatile uint32_t *const plic_priority = (uint32_t *)(0xc000000U);
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2025-01-15 15:44:29 +08:00
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2025-01-16 16:34:48 +08:00
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volatile uint32_t *plic_pending_0_31 = (uint32_t*)( 0xc000000U + 0X001000 );
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volatile uint32_t *plic_enable_0_31 = (uint32_t*)( 0xc000000U + 0X002000 );
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2025-01-15 15:44:29 +08:00
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2025-01-16 16:34:48 +08:00
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volatile uint32_t *plic_threshold_0 = (uint32_t*)( 0xc000000U + 0X200000 );
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volatile uint32_t *plic_claim = (uint32_t*)( 0xc000000U + 0X200004 );
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2025-02-10 00:03:16 +08:00
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static inline void error() {
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while(1);
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}
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2025-01-15 15:44:29 +08:00
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2025-02-10 00:03:16 +08:00
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extern const uint8_t int_svr_code[];
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uint32_t (*sys_call)(uint32_t no, ...);
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2025-01-15 15:44:29 +08:00
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2025-01-16 16:34:48 +08:00
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2025-01-15 15:44:29 +08:00
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2025-02-10 00:03:16 +08:00
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void main()
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{
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int i;
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/*初始化plic*/
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*plic_enable_0_31 = 1 << CDR_INT_TX0END
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| 1 << CDR_INT_TX1END
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| 1 << CDR_INT_RX0ERROR
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| 1 << CDR_INT_RX1ERROR
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| 1 << CDR_INT_RX0START
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| 1 << CDR_INT_RX1START
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| 1 << CDR_INT_RX0END
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| 1 << CDR_INT_RX1END
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//| 1 << CDR_INT_TX0_FIFO_DEQ
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//| 1 << CDR_INT_TX1_FIFO_DEQ
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| 1 << CDR_INT_RX0_FIFO_ENQ
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| 1 << CDR_INT_RX1_FIFO_ENQ
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;
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plic_priority[CDR_INT_TX0END] = 1;
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plic_priority[CDR_INT_TX1END] = 1;
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plic_priority[CDR_INT_RX0ERROR] = 1;
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plic_priority[CDR_INT_RX1ERROR] = 1;
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plic_priority[CDR_INT_RX0START] = 1;
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plic_priority[CDR_INT_RX1START] = 1;
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plic_priority[CDR_INT_RX0END] = 1;
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plic_priority[CDR_INT_RX1END] = 1;
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plic_priority[CDR_INT_TX0_FIFO_DEQ] = 1;
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plic_priority[CDR_INT_TX1_FIFO_DEQ] = 1;
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plic_priority[CDR_INT_RX0_FIFO_ENQ] = 1;
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plic_priority[CDR_INT_RX1_FIFO_ENQ] = 1;
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*plic_threshold_0 = 0;
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2025-01-15 15:44:29 +08:00
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2025-02-10 00:03:16 +08:00
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sys_call = (void *)int_svr_code;
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2025-01-16 16:34:48 +08:00
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2025-02-10 00:03:16 +08:00
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//复位脉冲
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*tx0_softReset = 1;
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*tx1_softReset = 1;
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*rx0_softReset = 1;
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*rx1_softReset = 1;
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2025-01-16 16:34:48 +08:00
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2025-02-10 00:03:16 +08:00
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//tx0 下行
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//tx1 上行
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//rx0 下行
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//rx1 上行
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2025-01-16 16:34:48 +08:00
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2024-10-29 17:32:17 +08:00
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2025-02-10 00:03:16 +08:00
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while (1);
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2024-10-29 17:32:17 +08:00
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2025-02-10 00:03:16 +08:00
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#if 0
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2024-11-15 14:35:39 +08:00
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register uint32_t readDat;
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register uint32_t operator;
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register uint32_t downRecvLen;
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register uint32_t upRecvLen;
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2025-01-16 16:34:48 +08:00
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register uint32_t crc;
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2024-11-15 14:35:39 +08:00
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2025-01-16 16:34:48 +08:00
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uint8_t localData[512];
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2024-10-30 17:51:33 +08:00
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uint32_t slvNum;
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uint32_t totNum;
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2024-11-15 14:35:39 +08:00
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register uint32_t isLast;
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register uint32_t flag;
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2025-01-27 22:25:39 +08:00
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*plic_enable_0_31 = 1 << CDR_INT_TXEND | 1 << CDR_INT_RXERROR | 1 << CDR_INT_RXSTART | 1 << CDR_INT_RXEND;
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*plic_priority_TxEnd = 1;
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*plic_priority_RxError = 1;
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*plic_priority_RxStart = 1;
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*plic_priority_RxEnd = 1;
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2025-01-16 16:34:48 +08:00
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*plic_threshold_0 = 0;
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2024-10-29 17:32:17 +08:00
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2024-11-05 17:48:34 +08:00
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2024-10-29 17:32:17 +08:00
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while(1){
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2025-01-16 16:34:48 +08:00
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*cdr_softReset = 1; //复位脉冲
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*cdr_direct = 0;
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2025-01-17 16:21:46 +08:00
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isLast = *cdr_IsLast;
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2024-10-29 17:32:17 +08:00
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2025-01-16 16:34:48 +08:00
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// asm volatile(
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// "sw x0, 0x10(x0)\n" //cdr_softReset 写入任意值进行复位//复位脉冲
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// "lw %0, 0x408(x0)\n" //ReadIsLast 获取是否为最后一个从机
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// "sw x0, 0xc(x0)\n" //设置CDR方向
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// : "+r"(isLast)
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// );
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2024-11-15 14:35:39 +08:00
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2024-12-02 15:00:03 +08:00
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// *WriteGpio = 0x01;
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2024-11-01 17:07:35 +08:00
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2024-11-15 14:35:39 +08:00
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//等待接收开始中断
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2025-01-17 16:21:46 +08:00
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while(!flag_intRxStart);
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2025-01-16 16:34:48 +08:00
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// asm volatile (
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// "1:\n"
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// "andi %0, sp, 0x04\n"
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// "beqz %0, 1b\n"
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// "andi sp, sp, 0xFB\n"
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// : "+r"(flag)
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// );
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readDat = *cdr_rxFifo;
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operator = (readDat >> 16) & 0xf;
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downRecvLen = readDat >> 20;
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readDat = *cdr_rxFifo;
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// asm volatile (
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// "lw %0, 0x1c(x0)\n" //read rxfifo
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// "srli %1, %0, 16\n" // operator = readDat >> 16
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// "srli %2, %1, 4\n" // downRecvLen = operator >> 4
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// "andi %1, %1,0xf\n" // operator = operator & 0xf
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// "lw %0, 0x1c(x0)\n" //read rxfifo
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// : "+r"(readDat), "+r"(operator), "+r"(downRecvLen)
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// );
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2024-11-15 14:35:39 +08:00
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2024-10-29 17:32:17 +08:00
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2024-12-02 15:00:03 +08:00
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// *WriteGpio = 0x03;
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2024-10-29 17:32:17 +08:00
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if( operator == 0 ){
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2024-11-04 16:47:01 +08:00
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2024-10-29 17:32:17 +08:00
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2024-11-15 14:35:39 +08:00
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2024-10-29 17:32:17 +08:00
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//接收本地包
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for( uint32_t i = 0; i < 2; i++ ) {
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if( flag_intRxError ){
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2025-01-16 16:34:48 +08:00
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while(1);
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}
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*(localData+i) = *cdr_rxFifo;
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// asm volatile (
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// "andi %0, sp, 0x08\n"
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// "1:\n"
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// "bnez %0, 1b\n" //error
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// "lw %1, 0x1c(x0)\n" //read rxfifo
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// : "+r"(flag), "+r"(readDat)
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// );
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2024-10-29 17:32:17 +08:00
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}
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2024-11-15 14:35:39 +08:00
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2024-12-02 15:00:03 +08:00
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// *WriteGpio = 0x07;
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2024-11-15 14:35:39 +08:00
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register uint32_t downSendLen;
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2025-01-17 16:21:46 +08:00
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downSendLen = downRecvLen - 8;
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2024-11-15 14:35:39 +08:00
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2024-10-30 17:51:33 +08:00
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if(!isLast){
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// 下行转发新建包头
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2024-11-15 14:35:39 +08:00
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register uint32_t downSendHead;
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2025-01-16 16:34:48 +08:00
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*cdr_txLen = downRecvLen;
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downSendHead = (downSendLen << 20) | ( 0 << 16) | 0;
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*cdr_txFifo = downSendHead;
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*cdr_txFifo = 0;
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// asm volatile (
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// "sw %0, 0x4(x0)\n" // *cdr_txLen = downRecvLen
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// "addi %2, %0, -8\n" //downSendLen = downRecvLen - 8;
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// "slli %1, %2, 20\n" // downSendHead = (downSendLen << 20) |( 0 << 16) | 0;
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// "sw %1, 0x8(x0)\n" //*cdr_txFifo = downSendHead
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// "sw x0, 0x8(x0)\n" //*cdr_txFifo = 0
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// : "+r"(downRecvLen), "+r"(downSendHead), "+r"(downSendLen)
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// );
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2024-10-29 17:32:17 +08:00
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2024-11-01 17:07:35 +08:00
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//下行转发负载
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2024-11-15 14:35:39 +08:00
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for( uint32_t i = 0; i < (downSendLen); i+=4 ){ //一次传4byte
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2024-11-05 17:48:34 +08:00
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register uint32_t forData;
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2025-01-16 16:34:48 +08:00
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if( flag_intRxError){
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while(1);
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}
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*cdr_txFifo = *cdr_rxFifo;
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// asm volatile (
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// "andi %0, sp, 0x08\n"
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// "1:\n"
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// "bnez %0, 1b\n" //error 速度不够,不再检查接收
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// "lw %1, 0x01c(x0)\n"
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// "sw %1, 0x008(x0)\n"
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// :
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// "+r"(flag), "+r"(forData)
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// );
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2024-10-30 17:51:33 +08:00
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}
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} else{ //isLast
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//空转掉剩余负载
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for( uint32_t i = 0; i < (downSendLen >> 2); i++ ){ //一次传4byte
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2024-11-05 17:48:34 +08:00
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register uint32_t forData;
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2025-01-16 16:34:48 +08:00
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if( flag_intRxError ){
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while(1);
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}
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readDat = *cdr_rxFifo;
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// asm volatile (
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// "andi %0, sp, 0x08\n"
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// "1:\n"
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// "bnez %0, 1b\n" //error 速度不够,不再检查接收
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// "lw %1, 0x01c(x0)\n"
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// : "+r"(flag), "+r"(forData)
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// );
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2024-10-30 17:51:33 +08:00
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}
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2024-10-29 17:32:17 +08:00
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}
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2024-11-05 17:48:34 +08:00
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2024-12-02 15:00:03 +08:00
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// *WriteGpio = 0x0f;
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2024-11-15 14:35:39 +08:00
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//CRC
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2025-01-16 16:34:48 +08:00
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if( flag_intRxError ){
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while(1);
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}
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crc = *cdr_rxFifo;
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// asm volatile (
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// "andi %0, sp, 0x08\n"
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// "1:\n"
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// "bnez %0, 1b\n" //error
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// "lw %1, 0x1c(x0)\n" //read rxfifo
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// : "+r"(flag), "+r"(readDat)
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// );
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2024-11-15 14:35:39 +08:00
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2024-12-02 15:00:03 +08:00
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// *WriteGpio = 0x1f;
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2024-10-29 17:32:17 +08:00
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2024-10-30 17:11:59 +08:00
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//等待接收完成标志
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2025-01-16 16:34:48 +08:00
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while(!flag_intRxEnd);
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flag_intRxEnd = 0;
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// asm volatile (
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// "1:\n"
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// "andi %0, sp, 0x08\n"
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// "beqz %0, 1b\n"
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// "andi sp, sp, 0xF7\n"
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// : "+r"(flag)
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// );
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2024-11-15 14:35:39 +08:00
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2024-12-02 15:00:03 +08:00
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// *WriteGpio = 0x3f;
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2024-10-29 17:32:17 +08:00
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2024-11-04 16:07:06 +08:00
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if(!isLast){
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//等待发送完成标志
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2025-01-16 16:34:48 +08:00
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while(!flag_intTxEnd);
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flag_intTxEnd = 0;
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// asm volatile (
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// "1:\n"
|
|
|
|
|
// "andi %0, sp, 0x01\n"
|
|
|
|
|
// "beqz %0, 1b\n"
|
|
|
|
|
// "andi sp, sp, 0xFE\n"
|
|
|
|
|
// :"+r"(flag)
|
|
|
|
|
// );
|
2024-11-04 16:07:06 +08:00
|
|
|
}
|
2024-11-01 17:07:35 +08:00
|
|
|
|
2024-12-02 15:00:03 +08:00
|
|
|
// *WriteGpio = 0x7f;
|
2024-11-01 17:07:35 +08:00
|
|
|
|
2024-11-15 14:35:39 +08:00
|
|
|
register uint32_t one = 1;
|
|
|
|
|
register uint32_t txLen;
|
|
|
|
|
register uint32_t txHeader;
|
2024-11-01 17:07:35 +08:00
|
|
|
|
2025-01-16 16:34:48 +08:00
|
|
|
*cdr_softReset = 1;
|
|
|
|
|
*cdr_direct = 1;
|
|
|
|
|
// asm volatile(
|
|
|
|
|
// "sw x0, 0x10(x0)\n" //cdr_softReset 写入任意值进行复位//复位脉冲
|
|
|
|
|
// "sw %0, 0xc(x0)\n" //设置CDR方向
|
|
|
|
|
// : "+r"(one)
|
|
|
|
|
// );
|
2024-11-01 17:07:35 +08:00
|
|
|
|
|
|
|
|
|
2024-10-30 17:51:33 +08:00
|
|
|
if(!isLast){
|
|
|
|
|
//上行转发
|
2024-10-29 17:32:17 +08:00
|
|
|
|
2024-10-30 17:51:33 +08:00
|
|
|
//接收第一个包
|
2025-01-16 16:34:48 +08:00
|
|
|
|
|
|
|
|
while(!flag_intRxStart);
|
|
|
|
|
flag_intRxStart = 0;
|
|
|
|
|
// asm volatile (
|
|
|
|
|
// "1:\n"
|
|
|
|
|
// "andi %0, sp, 0x04\n"
|
|
|
|
|
// "beqz %0, 1b\n"
|
|
|
|
|
// "andi sp, sp, 0xFB\n"
|
|
|
|
|
// :"+r"(flag)
|
|
|
|
|
// );
|
2024-11-04 16:07:06 +08:00
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2025-01-16 16:34:48 +08:00
|
|
|
//接收第一个包
|
|
|
|
|
if(flag_intRxError){while(1);}
|
|
|
|
|
readDat = *cdr_rxFifo;
|
|
|
|
|
upRecvLen = readDat >> 20;
|
|
|
|
|
txLen = upRecvLen + 16;
|
|
|
|
|
txHeader = upRecvLen + 8;
|
|
|
|
|
txHeader = (txHeader << 20) | ( 0 << 16) | 0;
|
|
|
|
|
|
2024-11-15 14:35:39 +08:00
|
|
|
//发送上行包头
|
2025-01-16 16:34:48 +08:00
|
|
|
*cdr_txLen = txLen;
|
|
|
|
|
*cdr_txFifo = txHeader;
|
|
|
|
|
*cdr_txFifo = 0;
|
|
|
|
|
|
|
|
|
|
// asm volatile (
|
|
|
|
|
// "lw %0, 0x1c(x0)\n" //read rxfifo
|
|
|
|
|
// "srli %1, %0, 20\n" // upRecvLen = readDat >> 20
|
|
|
|
|
// "addi %2, %1, 16\n" //txLen = upRecvLen + 16
|
|
|
|
|
// "addi %3, %1, 8\n" //txHeader = upRecvLen + 8
|
|
|
|
|
// "slli %3, %3, 20\n" //txHeader = txHeader << 20 |( 0 << 16) | 0
|
|
|
|
|
// "sw %2, 0x4(x0)\n" //*cdr_txLen = txLen
|
|
|
|
|
// "sw %3, 0x8(x0)\n" //*cdr_txFifo = txHeader
|
|
|
|
|
// "sw x0, 0x8(x0)\n" //*cdr_txFifo = 0
|
|
|
|
|
|
|
|
|
|
// : "+r"(readDat), "+r"(upRecvLen), "+r"( txLen ), "+r"( txHeader )
|
|
|
|
|
// );
|
2024-11-04 16:07:06 +08:00
|
|
|
|
2024-11-15 14:35:39 +08:00
|
|
|
|
2024-10-30 17:51:33 +08:00
|
|
|
|
2024-10-29 17:32:17 +08:00
|
|
|
|
2024-11-04 16:07:06 +08:00
|
|
|
for( uint32_t i = 0; i < 8/4; i ++ ){
|
2025-01-16 16:34:48 +08:00
|
|
|
*cdr_txFifo = 0;
|
|
|
|
|
// asm volatile (
|
|
|
|
|
// "sw x0, 0x8(x0)\n" //*cdr_txFifo = 0;
|
|
|
|
|
// );
|
2024-10-30 17:51:33 +08:00
|
|
|
}
|
|
|
|
|
|
2024-11-04 16:07:06 +08:00
|
|
|
|
|
|
|
|
|
|
|
|
|
//接收第二个包
|
2025-01-16 16:34:48 +08:00
|
|
|
if(flag_intRxError){while(1);}
|
|
|
|
|
readDat = *cdr_rxFifo;
|
|
|
|
|
// asm volatile (
|
|
|
|
|
// "andi %0, sp, 0x08\n"
|
|
|
|
|
// "1:\n"
|
|
|
|
|
// "bnez %0, 1b\n" //error //速度不够,不校验
|
|
|
|
|
// "lw %1, 0x1c(x0)\n" //read rxfifo
|
|
|
|
|
// :"+r"(flag), "+r"(readDat)
|
|
|
|
|
// );
|
2024-11-15 14:35:39 +08:00
|
|
|
|
2024-11-04 16:07:06 +08:00
|
|
|
|
|
|
|
|
|
2024-10-30 17:51:33 +08:00
|
|
|
//上行转发负载
|
2024-11-15 14:35:39 +08:00
|
|
|
for( uint32_t i = 0; i < (upRecvLen); i += 4 ){ //一次传4byte
|
2024-11-05 17:48:34 +08:00
|
|
|
register uint32_t forData;
|
2025-01-16 16:34:48 +08:00
|
|
|
|
|
|
|
|
if( flag_intRxError ){
|
|
|
|
|
while(1);
|
|
|
|
|
}
|
|
|
|
|
*cdr_txFifo = *cdr_rxFifo;
|
|
|
|
|
|
|
|
|
|
// asm volatile (
|
|
|
|
|
// "andi %0, sp, 0x80\n"
|
|
|
|
|
// "1:\n"
|
|
|
|
|
// "bnez %0, 1b\n" //error 速度不够,不再检查接收
|
|
|
|
|
// "lw %1, 0x01c(x0)\n"
|
|
|
|
|
// "sw %1, 0x008(x0)\n"
|
|
|
|
|
// :"+r"(flag), "+r"(forData)
|
|
|
|
|
// );
|
2024-10-30 17:51:33 +08:00
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
//CRC
|
2025-01-16 16:34:48 +08:00
|
|
|
if( flag_intRxError ){
|
|
|
|
|
while(1);
|
|
|
|
|
}
|
|
|
|
|
crc = *cdr_rxFifo;
|
|
|
|
|
// asm volatile (
|
|
|
|
|
// "andi %0, sp, 0x08\n"
|
|
|
|
|
// "1:\n"
|
|
|
|
|
// "bnez %0, 1b\n" //error
|
|
|
|
|
// "lw %0, 0x1c(x0)\n" //read rxfifo
|
|
|
|
|
// :"+r"(flag), "+r"(readDat)
|
|
|
|
|
// );
|
2024-11-15 14:35:39 +08:00
|
|
|
|
2024-10-30 17:51:33 +08:00
|
|
|
|
|
|
|
|
//等待接收完成标志
|
2025-01-16 16:34:48 +08:00
|
|
|
while(!flag_intRxEnd);
|
|
|
|
|
flag_intRxEnd = 0;
|
|
|
|
|
// asm volatile (
|
|
|
|
|
// "1:\n"
|
|
|
|
|
// "andi %0, sp, 0x08\n"
|
|
|
|
|
// "beqz %0, 1b\n"
|
|
|
|
|
// "andi sp, sp, 0xF7\n"
|
|
|
|
|
// :"+r"(flag)
|
|
|
|
|
// );
|
2024-10-29 17:32:17 +08:00
|
|
|
|
2024-11-04 16:07:06 +08:00
|
|
|
totNum = slvNum + (upRecvLen >> 3) - 1;
|
2024-10-30 17:51:33 +08:00
|
|
|
} else { //islast
|
2024-11-15 14:35:39 +08:00
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2024-10-30 17:51:33 +08:00
|
|
|
//发送上行包头
|
2025-01-16 16:34:48 +08:00
|
|
|
txLen = upRecvLen + 16;
|
|
|
|
|
txHeader = ( 8 << 20 ) | ( 0 << 16) | 0;
|
|
|
|
|
*cdr_txLen = txLen;
|
|
|
|
|
*cdr_txFifo = txHeader;
|
|
|
|
|
*cdr_txFifo = 0;
|
|
|
|
|
// asm volatile (
|
|
|
|
|
|
|
|
|
|
// "li %0, 16\n" //txLen = upRecvLen + 16
|
|
|
|
|
// "sw %0, 0x4(x0)\n" //*cdr_txLen = txLen
|
|
|
|
|
// "lui %1, 0x800\n" //txHeader = 8 << 20 |( 0 << 16) | 0
|
|
|
|
|
// "sw %1, 0x8(x0)\n" //*cdr_txFifo = txHeader
|
|
|
|
|
// "sw x0, 0x8(x0)\n" //*cdr_txFifo = 0
|
|
|
|
|
|
|
|
|
|
// : "+r"( txLen ), "+r"( txHeader )
|
|
|
|
|
// );
|
2024-10-30 17:51:33 +08:00
|
|
|
|
2024-11-04 16:07:06 +08:00
|
|
|
for( uint32_t i = 0; i < 8/4; i ++ ){
|
2025-01-16 16:34:48 +08:00
|
|
|
*cdr_txFifo = 0;
|
|
|
|
|
// asm volatile (
|
|
|
|
|
// "sw x0, 0x8(x0)\n" //*cdr_txFifo = 0;
|
|
|
|
|
// );
|
2024-10-30 17:51:33 +08:00
|
|
|
}
|
2024-11-04 16:07:06 +08:00
|
|
|
}
|
|
|
|
|
|
2024-11-04 16:47:01 +08:00
|
|
|
//等待发送完成标志
|
2025-01-16 16:34:48 +08:00
|
|
|
while(!flag_intTxEnd);
|
|
|
|
|
flag_intTxEnd = 0;
|
|
|
|
|
// asm volatile (
|
|
|
|
|
// "1:\n"
|
|
|
|
|
// "andi %0, sp, 0x01\n"
|
|
|
|
|
// "beqz %0, 1b\n"
|
|
|
|
|
// "andi sp, sp, 0xFE\n"
|
|
|
|
|
// :"+r"(flag)
|
|
|
|
|
// );
|
2024-10-30 17:51:33 +08:00
|
|
|
|
2024-11-04 16:47:01 +08:00
|
|
|
slvNum = 64 - ( downRecvLen >> 3 );
|
2025-01-17 16:21:46 +08:00
|
|
|
// *WriteGpio = 1 << slvNum;
|
2024-10-29 17:32:17 +08:00
|
|
|
|
|
|
|
|
} else if ( operator == 1 ){
|
2024-11-05 17:48:34 +08:00
|
|
|
// error();
|
2024-10-29 17:32:17 +08:00
|
|
|
} else if ( operator == 2 ){
|
2024-11-05 17:48:34 +08:00
|
|
|
// error();
|
2024-10-29 17:32:17 +08:00
|
|
|
} else {
|
2024-11-05 17:48:34 +08:00
|
|
|
// error();
|
2024-10-29 17:32:17 +08:00
|
|
|
}
|
|
|
|
|
}
|
2025-02-10 00:03:16 +08:00
|
|
|
#endif
|
2024-10-29 17:32:17 +08:00
|
|
|
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|