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eb001/tb/sw/src/mstStartup.S

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ArmAsm
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#include "tl2cdr.h"
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.extern main
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.extern plic_handle
.extern int_svr_code
.extern plic_claim
.extern flag_intTxEnd
.extern flag_intRxError
.extern flag_intRxStart
.extern flag_intRxEnd
.globl _prog_start
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.section .text.init
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_prog_start:
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li x1, 0
li x2, 0
li x3, 0
li x4, 0
li x5, 0
li x6, 0
li x7, 0
li x8, 0
li x9, 0
li x10, 0
li x11, 0
li x12, 0
li x13, 0
li x14, 0
li x15, 0
#ifdef __RV32I_MARCH__
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li x16, 0
li x17, 0
li x18, 0
li x19, 0
li x20, 0
li x21, 0
li x22, 0
li x23, 0
li x24, 0
li x25, 0
li x26, 0
li x27, 0
li x28, 0
li x29, 0
li x30, 0
li x31, 0
#endif
li sp, 0x40011000
lui t0, %hi(plic_claim)
lw a0, %lo(plic_claim)(t0)
#la a0, plic_claim
#lui t0, %hi(flag_intTxEnd)
#lw a1, %lo(flag_intTxEnd)(t0)
la a1, flag_intTxEnd
#lui t0, %hi(flag_intRxError)
#lw a2, %lo(flag_intRxError)(t0)
la a2, flag_intRxError
#lui t0, %hi(flag_intRxStart)
#lw a3, %lo(flag_intRxStart)(t0)
la a3, flag_intRxStart
#lui t0, %hi(flag_intRxEnd)
#lw a4, %lo(flag_intRxEnd)(t0)
la a4, flag_intRxEnd
call int_svr_code
mv t0, a0 #trap_entry,RV32I
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#la t0, trap_entry #trap_entryRV32E
#la t0, opt_trap_entry #RV32E
csrw mtvec, t0
li t0, 1 << 11
csrw mie, t0
csrr t0, mstatus
ori t0, t0, 1<<3
csrw mstatus, t0
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call main
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ecall
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.balign 32
.section .trap_entry, "ax", %progbits
trap_entry:
addi sp,sp,-136
sw ra,4(sp)
sw sp,8(sp)
sw gp,12(sp)
sw tp,16(sp)
sw t0,20(sp)
sw t1,24(sp)
sw t2,28(sp)
sw s0,32(sp)
sw s1,36(sp)
sw a0,40(sp)
sw a1,44(sp)
sw a2,48(sp)
sw a3,52(sp)
sw a4,56(sp)
sw a5,60(sp)
#ifdef __RV32I_MARCH__
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sw a6,64(sp)
sw a7,68(sp)
sw s2,72(sp)
sw s3,76(sp)
sw s4,80(sp)
sw s5,84(sp)
sw s6,88(sp)
sw s7,92(sp)
sw s8,96(sp)
sw s9,100(sp)
sw s10,104(sp)
sw s11,108(sp)
sw t3,112(sp)
sw t4,116(sp)
sw t5,120(sp)
sw t6,124(sp)
#endif
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#if 0
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csrr t0, mstatus # mstatus
andi t0, t0, ~(1 << 3) # MIE ()
csrw mstatus, t0 # mstatus
#endif
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call plic_handle
#if 0
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csrr t0, mstatus
ori t0, t0, 1<<3
csrw mstatus, t0
#endif
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lw ra,4(sp)
lw sp,8(sp)
lw gp,12(sp)
lw tp,16(sp)
lw t0,20(sp)
lw t1,24(sp)
lw t2,28(sp)
lw s0,32(sp)
lw s1,36(sp)
lw a0,40(sp)
lw a1,44(sp)
lw a2,48(sp)
lw a3,52(sp)
lw a4,56(sp)
lw a5,60(sp)
#ifdef __RV32I_MARCH__
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lw a6,64(sp)
lw a7,68(sp)
lw s2,72(sp)
lw s3,76(sp)
lw s4,80(sp)
lw s5,84(sp)
lw s6,88(sp)
lw s7,92(sp)
lw s8,96(sp)
lw s9,100(sp)
lw s10,104(sp)
lw s11,108(sp)
lw t3,112(sp)
lw t4,116(sp)
lw t5,120(sp)
lw t6,124(sp)
#endif
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addi sp,sp,136
mret
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#.macro define_const name, value
# .equ \name, \value
#.endm
## 使
#define_const CDR_INT_TXEND, 14
opt_trap_entry:
addi sp,sp,-136
#sw ra,4(sp)
#sw sp,8(sp)
#sw gp,12(sp)
#sw tp,16(sp)
sw t0,20(sp)
sw t1,24(sp)
#sw t2,28(sp)
sw s0,32(sp)
sw s1,36(sp)
#sw a0,40(sp)
#sw a1,44(sp)
#sw a2,48(sp)
#sw a3,52(sp)
#sw a4,56(sp)
#sw a5,60(sp)
#sw a6,64(sp)
#sw a7,68(sp)
#sw s2,72(sp)
#sw s3,76(sp)
#sw s4,80(sp)
#sw s5,84(sp)
#sw s6,88(sp)
#sw s7,92(sp)
#sw s8,96(sp)
#sw s9,100(sp)
#sw s10,104(sp)
#sw s11,108(sp)
#sw t3,112(sp)
#sw t4,116(sp)
#sw t5,120(sp)
#sw t6,124(sp)
#if 0
csrr t0, mstatus # mstatus
andi t0, t0, ~(1 << 3) # MIE ()
csrw mstatus, t0 # mstatus
#endif
lui t1, %hi(plic_claim)
lw t0, %lo(plic_claim)(t1) # t0 = &plic_claim
lw t1, 0(t0) # t1 = *plic_claim
sw t1, 0(t0) # *plic_claim = t1
li s0, CDR_INT_TXEND
bne t1, s0, 1f #_if (t1 != s0) goto 1f
lui s0,%hi(flag_intTxEnd) #_else
li s1,1
sw s1,%lo(flag_intTxEnd)(s0)
j 4f
1:
li s0, CDR_INT_RXERROR
bne t1, s0, 2f #_if (t1 != s0) goto 2f
lui s0,%hi(flag_intRxError) #_else
li s1,1
sw s1,%lo(flag_intRxError)(s0)
j 4f
2:
li s0, CDR_INT_RXSTART
bne t1, s0, 3f #_if (t1 != s0) goto 3f
lui s0,%hi(flag_intRxStart) #_else
li s1,1
sw s1,%lo(flag_intRxStart)(s0)
j 4f
3:
li s0, CDR_INT_RXEND
bne t1, s0, 4f #_if (t1 != s0) goto 4f
lui s0,%hi(flag_intRxEnd) #_else
li s1,1
sw s1,%lo(flag_intRxEnd)(s0)
4:
#if 0
csrr t0, mstatus
ori t0, t0, 1<<3
csrw mstatus, t0
#endif
#lw ra,4(sp)
#lw sp,8(sp)
#lw gp,12(sp)
#lw tp,16(sp)
lw t0,20(sp)
lw t1,24(sp)
#lw t2,28(sp)
lw s0,32(sp)
lw s1,36(sp)
#lw a0,40(sp)
#lw a1,44(sp)
#lw a2,48(sp)
#lw a3,52(sp)
#lw a4,56(sp)
#lw a5,60(sp)
#lw a6,64(sp)
#lw a7,68(sp)
#lw s2,72(sp)
#lw s3,76(sp)
#lw s4,80(sp)
#lw s5,84(sp)
#lw s6,88(sp)
#lw s7,92(sp)
#lw s8,96(sp)
#lw s9,100(sp)
#lw s10,104(sp)
#lw s11,108(sp)
#lw t3,112(sp)
#lw t4,116(sp)
#lw t5,120(sp)
#lw t6,124(sp)
addi sp,sp,136
mret
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