218 lines
4.1 KiB
Verilog
218 lines
4.1 KiB
Verilog
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/*
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Copyright (c) 2020 - 2023 Wuhan University of Technology <295054118@whut.edu.cn>
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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module SimTop (
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// output success,
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// output fail,
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input clock, //100MHz
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input reset,
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input clk400,
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input uDatIn,
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output uDatOut,
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input dDatIn,
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output dDatOut
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);
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wire dmactive;
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ExampleRocketSystem s_rocket(
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.clock(clock),
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.reset(reset),
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.resetctrl_hartIsInReset_0(reset),
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.debug_clock(clock),
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.debug_reset(reset),
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.debug_systemjtag_jtag_TCK(1'b0),
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.debug_systemjtag_jtag_TMS(1'b0),
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.debug_systemjtag_jtag_TDI(1'b0),
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.debug_systemjtag_jtag_TDO_data(),
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.debug_systemjtag_jtag_TDO_driven(),
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.debug_systemjtag_reset(reset),
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.debug_systemjtag_mfr_id(11'b0),
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.debug_systemjtag_part_number(16'b0),
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.debug_systemjtag_version(4'b0),
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.debug_ndreset(),
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.debug_dmactive(dmactive),
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.debug_dmactiveAck(dmactive),
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.mmio_apb_0_psel(),
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.mmio_apb_0_penable(),
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.mmio_apb_0_pwrite(),
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.mmio_apb_0_paddr(),
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.mmio_apb_0_pprot(),
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.mmio_apb_0_pwdata(),
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.mmio_apb_0_pstrb(),
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.mmio_apb_0_pready(1'b1),
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.mmio_apb_0_pslverr(1'b0),
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.mmio_apb_0_prdata(32'b0),
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.mmio_ahb_0_hmastlock(),
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.mmio_ahb_0_hsel(),
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.mmio_ahb_0_hready(),
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.mmio_ahb_0_hreadyout(1'b1),
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.mmio_ahb_0_htrans(),
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.mmio_ahb_0_hsize(),
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.mmio_ahb_0_hburst(),
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.mmio_ahb_0_hwrite(),
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.mmio_ahb_0_hprot(),
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.mmio_ahb_0_haddr(),
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.mmio_ahb_0_hwdata(),
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.mmio_ahb_0_hresp(2'b0),
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.mmio_ahb_0_hrdata(32'b0),
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.mmio_ahb_0_hmaster(),
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.mmio_ahb_0_hsplit(16'b0),
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.interrupts(2'b0),
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.cdrio_overCLK(clk400),
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.cdrio_uDatIn(uDatIn),
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.cdrio_uDatOut(uDatOut),
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.cdrio_dDatIn(dDatIn),
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.cdrio_dDatOut(dDatOut)
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);
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// wire debugger_success;
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// debuger i_debuger(
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// .success(debugger_success),
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// .DEBUGER_AWID (mmio_axi4_0_aw_bits_id),
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// .DEBUGER_BID (mmio_axi4_0_b_bits_id),
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// .DEBUGER_ARID (mmio_axi4_0_ar_bits_id),
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// .DEBUGER_RID (mmio_axi4_0_r_bits_id),
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// .DEBUGER_AWADDR (mmio_axi4_0_aw_bits_addr),
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// .DEBUGER_AWVALID(mmio_axi4_0_aw_valid),
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// .DEBUGER_AWREADY(mmio_axi4_0_aw_ready),
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// .DEBUGER_WDATA (mmio_axi4_0_w_bits_data),
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// .DEBUGER_WSTRB (mmio_axi4_0_w_bits_strb),
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// .DEBUGER_WVALID(mmio_axi4_0_w_valid),
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// .DEBUGER_WREADY(mmio_axi4_0_w_ready),
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// .DEBUGER_BRESP (mmio_axi4_0_b_bits_resp),
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// .DEBUGER_BVALID(mmio_axi4_0_b_valid),
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// .DEBUGER_BREADY(mmio_axi4_0_b_ready),
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// .DEBUGER_ARADDR (mmio_axi4_0_ar_bits_addr),
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// .DEBUGER_ARVALID(mmio_axi4_0_ar_valid),
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// .DEBUGER_ARREADY(mmio_axi4_0_ar_ready),
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// .DEBUGER_RDATA (mmio_axi4_0_r_bits_data),
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// .DEBUGER_RRESP (mmio_axi4_0_r_bits_resp),
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// .DEBUGER_RVALID(mmio_axi4_0_r_valid),
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// .DEBUGER_RREADY(mmio_axi4_0_r_ready),
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// .CLK(CLK),
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// .RSTn(RSTn)
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// );
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reg [1023:0] firmware_file;
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initial begin
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if ($value$plusargs("%s", firmware_file)) begin
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$display("%s", firmware_file);
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$readmemh(firmware_file, s_rocket.ram.Mem_SRAM.Mem_SRAM_ext.ram);
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end
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end
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// assign success = debugger_success;
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// string testName;
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// `define MEM s_axi_full_slv_sram.i_sram.ram
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// reg [7:0] mem [0:200000];
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// localparam DP = 2**18;
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// integer i, by;
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// initial begin
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// #20
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// if ( $value$plusargs("%s",testName) ) begin
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// $display("%s",testName);
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// $readmemh(testName, mem);
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// end
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// else begin
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// $display("%s",testName);
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// $error("Failed to read Files!");
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// end
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// for ( i = 0; i < DP; i = i + 1 ) begin
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// for ( by = 0; by < 4; by = by + 1 ) begin
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// if ( | mem[i*4+by] ) begin
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// `MEM[i][8*by +: 8] = mem[i*4+by];
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// end
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// else begin
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// `MEM[i][8*by +: 8] = 8'h0;
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// end
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// end
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// end
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// end
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endmodule
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