/*
  Copyright (c) 2020 - 2023 Wuhan University of Technology <295054118@whut.edu.cn>

   Licensed under the Apache License, Version 2.0 (the "License");
   you may not use this file except in compliance with the License.
   You may obtain a copy of the License at

	   http://www.apache.org/licenses/LICENSE-2.0

   Unless required by applicable law or agreed to in writing, software
   distributed under the License is distributed on an "AS IS" BASIS,
   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
   See the License for the specific language governing permissions and
   limitations under the License.
*/






module SimTop (

	// output success,
	// output fail,

	input clock, //100MHz
	input reset,
  input clk400,

  input  uDatIn,
  output uDatOut,
  input  dDatIn,
  output dDatOut
);







wire dmactive;

ExampleRocketSystem s_rocket(
  .clock(clock),
  .reset(reset),
  .resetctrl_hartIsInReset_0(reset),

  .debug_clock(clock),
  .debug_reset(reset),
  .debug_systemjtag_jtag_TCK(1'b0),
  .debug_systemjtag_jtag_TMS(1'b0),
  .debug_systemjtag_jtag_TDI(1'b0),
  .debug_systemjtag_jtag_TDO_data(),
  .debug_systemjtag_jtag_TDO_driven(),
  .debug_systemjtag_reset(reset),
  .debug_systemjtag_mfr_id(11'b0),
  .debug_systemjtag_part_number(16'b0),
  .debug_systemjtag_version(4'b0),
  .debug_ndreset(),
  .debug_dmactive(dmactive),
  .debug_dmactiveAck(dmactive),

  .mmio_apb_0_psel(),
  .mmio_apb_0_penable(),
  .mmio_apb_0_pwrite(),
  .mmio_apb_0_paddr(),
  .mmio_apb_0_pprot(),
  .mmio_apb_0_pwdata(),
  .mmio_apb_0_pstrb(),
  .mmio_apb_0_pready(1'b1),
  .mmio_apb_0_pslverr(1'b0),
  .mmio_apb_0_prdata(32'b0),

  .mmio_ahb_0_hmastlock(),
  .mmio_ahb_0_hsel(),
  .mmio_ahb_0_hready(),
  .mmio_ahb_0_hreadyout(1'b1),
  .mmio_ahb_0_htrans(),
  .mmio_ahb_0_hsize(),
  .mmio_ahb_0_hburst(),
  .mmio_ahb_0_hwrite(),
  .mmio_ahb_0_hprot(),
  .mmio_ahb_0_haddr(),
  .mmio_ahb_0_hwdata(),
  .mmio_ahb_0_hresp(2'b0),
  .mmio_ahb_0_hrdata(32'b0),
  .mmio_ahb_0_hmaster(),
  .mmio_ahb_0_hsplit(16'b0),

  .interrupts(2'b0),

  .cdrio_overCLK(clk400),
  .cdrio_uDatIn(uDatIn),
  .cdrio_uDatOut(uDatOut),
  .cdrio_dDatIn(dDatIn),
  .cdrio_dDatOut(dDatOut)
);






// wire debugger_success;

// debuger i_debuger(
//   .success(debugger_success),
// 	.DEBUGER_AWID   (mmio_axi4_0_aw_bits_id),
// 	.DEBUGER_BID    (mmio_axi4_0_b_bits_id),
// 	.DEBUGER_ARID   (mmio_axi4_0_ar_bits_id),
// 	.DEBUGER_RID    (mmio_axi4_0_r_bits_id),

// 	.DEBUGER_AWADDR (mmio_axi4_0_aw_bits_addr),
// 	.DEBUGER_AWVALID(mmio_axi4_0_aw_valid),
// 	.DEBUGER_AWREADY(mmio_axi4_0_aw_ready),

// 	.DEBUGER_WDATA (mmio_axi4_0_w_bits_data),   
// 	.DEBUGER_WSTRB (mmio_axi4_0_w_bits_strb),
// 	.DEBUGER_WVALID(mmio_axi4_0_w_valid),
// 	.DEBUGER_WREADY(mmio_axi4_0_w_ready),

// 	.DEBUGER_BRESP (mmio_axi4_0_b_bits_resp),
// 	.DEBUGER_BVALID(mmio_axi4_0_b_valid),
// 	.DEBUGER_BREADY(mmio_axi4_0_b_ready),

// 	.DEBUGER_ARADDR (mmio_axi4_0_ar_bits_addr),
// 	.DEBUGER_ARVALID(mmio_axi4_0_ar_valid),
// 	.DEBUGER_ARREADY(mmio_axi4_0_ar_ready),

// 	.DEBUGER_RDATA (mmio_axi4_0_r_bits_data),
// 	.DEBUGER_RRESP (mmio_axi4_0_r_bits_resp),
// 	.DEBUGER_RVALID(mmio_axi4_0_r_valid),
// 	.DEBUGER_RREADY(mmio_axi4_0_r_ready),

// 	.CLK(CLK),
// 	.RSTn(RSTn)
	
// );




    
	reg [1023:0] firmware_file;
	initial begin
		if ($value$plusargs("%s", firmware_file)) begin
			$display("%s", firmware_file);
			$readmemh(firmware_file, s_rocket.ram.Mem_SRAM.Mem_SRAM_ext.ram);
		end
	end








// assign success = debugger_success;




// string testName;

// `define MEM s_axi_full_slv_sram.i_sram.ram
// reg [7:0] mem [0:200000];

// localparam DP = 2**18;
// integer i, by;
// initial begin

// #20

// 	if ( $value$plusargs("%s",testName) ) begin
// 		$display("%s",testName);
// 	  $readmemh(testName, mem);		

// 	end
// 	else begin 
//     $display("%s",testName);
// 		$error("Failed to read Files!");
// 	end

	
// 	for ( i = 0; i < DP; i = i + 1 ) begin
// 		for ( by = 0; by < 4; by = by + 1 ) begin
// 			if ( | mem[i*4+by] ) begin
// 				`MEM[i][8*by +: 8] = mem[i*4+by];
// 			end
// 			else begin
// 				`MEM[i][8*by +: 8] = 8'h0;
// 			end
// 		end
// 	end



// end 





endmodule