RuigeLee
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5ff118f527
|
rx: big-endian to little-endian
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2023-09-21 16:55:22 +08:00 |
|
RuigeLee
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e42c6a3b11
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dma cache to sys-port
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2023-09-20 11:17:30 +08:00 |
|
RuigeLee
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8a9aa0436c
|
a sign for tx/rx clock merge
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2023-09-19 18:03:30 +08:00 |
|
RuigeLee
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4702991e69
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tx: big-endian to little-endian
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2023-09-19 17:54:36 +08:00 |
|
RuigeLee
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40b558d3a2
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sync
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2023-09-15 15:36:44 +08:00 |
|
RuigeLee
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b098ca963e
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test pass
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2023-09-14 19:16:17 +08:00 |
|
RuigeLee
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6fd836fc9c
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new version
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2023-09-12 17:51:32 +08:00 |
|
RuigeLee
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527f6bd761
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fix sync misunderstanding
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2023-09-11 17:39:19 +08:00 |
|
RuigeLee
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05a905ac39
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merge mirror read/write
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2023-09-08 18:47:13 +08:00 |
|
RuigeLee
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bf835014bc
|
16bit fsmc data; 16*2 reg, 100us
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2023-09-08 16:37:31 +08:00 |
|
RuigeLee
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145db92202
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test pass
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2023-08-31 17:39:12 +08:00 |
|
RuigeLee
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d226487a5e
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BUG FIX
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2023-08-31 15:10:18 +08:00 |
|
RuigeLee
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860e24ca99
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check mst
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2023-08-30 17:32:19 +08:00 |
|
RuigeLee
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c0645cfe16
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update sram; bug fixed; lvds failed
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2023-08-23 19:32:41 +08:00 |
|
Ruige Lee (WSL)
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cead446356
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io merge
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2023-08-22 17:50:31 +08:00 |
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Ruige Lee (WSL)
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44e8999ab0
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switch from 4k to 2k
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2023-08-22 15:32:01 +08:00 |
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Ruige Lee (WSL)
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704996bdfb
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Merge branch 'main' of github.com:whutddk/RISCV-MAC-SWICH into main
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2023-08-22 14:17:55 +08:00 |
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RuigeLee
|
a3ce58fb94
|
add fpga top
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2023-08-21 21:14:43 +08:00 |
|
Ruige Lee (WSL)
|
37ac7817d7
|
fix sram
|
2023-08-21 14:52:21 +08:00 |
|
RuigeLee
|
5f15e94ae3
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bug override
|
2023-08-21 11:51:59 +08:00 |
|
RuigeLee
|
31a822091b
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Revert "devide gowin file"
This reverts commit d162b8f75c.
|
2023-08-21 11:51:25 +08:00 |
|
RuigeLee
|
d162b8f75c
|
devide gowin file
|
2023-08-21 11:46:50 +08:00 |
|
RuigeLee
|
20ddabbfb3
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add submodule
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2023-08-21 11:20:16 +08:00 |
|
RuigeLee
|
589fc528a0
|
compile pass
|
2023-08-20 15:50:11 +08:00 |
|
Ruige Lee
|
f3a44f0b31
|
slv
|
2023-08-18 12:10:47 +00:00 |
|
RuigeLee
|
6fa2ef5f6e
|
porta
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2023-08-16 22:25:30 +08:00 |
|
Ruige Lee
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bbd0f0b887
|
sync
|
2023-08-16 06:12:49 +00:00 |
|
Ruige Lee
|
6c2f0b02f8
|
FSMC
|
2023-08-15 08:42:56 +00:00 |
|
Ruige Lee
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939fa22be5
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wrapper of mst and slv
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2023-08-15 02:59:10 +00:00 |
|
RuigeLee
|
3211e21e11
|
wrapper
|
2023-08-14 22:46:50 +08:00 |
|
RuigeLee
|
50403930a9
|
check chain
|
2023-08-09 16:34:29 +08:00 |
|
RuigeLee
|
1c7a226a70
|
add function demo
|
2023-08-09 14:43:24 +08:00 |
|
RuigeLee
|
68e0a6a055
|
test pass
|
2023-08-07 11:40:14 +08:00 |
|
RuigeLee
|
a041c7732a
|
over sample in spi
|
2023-08-07 10:15:56 +08:00 |
|
RuigeLee
|
d09aff40f2
|
timing close
|
2023-08-02 15:17:16 +08:00 |
|
RuigeLee
|
5d43600680
|
fpga sync
|
2023-08-01 15:50:53 +08:00 |
|
RuigeLee
|
35e6fcdb52
|
mst test pass
|
2023-08-01 14:44:05 +08:00 |
|
RuigeLee
|
24800cce9d
|
spi compile pass
|
2023-07-31 22:56:09 +08:00 |
|
RuigeLee
|
0f79860656
|
revert mdio direction
|
2023-07-31 09:19:57 +08:00 |
|
RuigeLee
|
3aa4ca17d4
|
all test pass
|
2023-07-28 20:42:35 +08:00 |
|
RuigeLee
|
2048a4d286
|
first test
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2023-07-28 15:38:46 +08:00 |
|
Ruige
|
85fe9175e6
|
backplaneslv compile pass
Signed-off-by: Ruige <295054118@whut.edu.cn>
|
2023-07-25 21:05:43 +08:00 |
|
RuigeLee
|
b1fd2db2e0
|
backboard
|
2023-07-24 19:31:32 +08:00 |
|
RuigeLee
|
440cefb02a
|
we use async reset for different clock now
|
2023-07-24 19:31:20 +08:00 |
|
RuigeLee
|
21f8547273
|
ethreg Test pass
|
2023-07-21 16:38:02 +08:00 |
|
RuigeLee
|
0b48e2cd2b
|
compile pass
|
2023-07-20 14:58:59 +08:00 |
|
RuigeLee
|
fa748b7de9
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Revert "create register node"
This reverts commit e558356a22.
|
2023-07-20 10:35:56 +08:00 |
|
RuigeLee
|
e558356a22
|
create register node
|
2023-07-20 10:01:59 +08:00 |
|
RuigeLee
|
6cb9d0982e
|
tb remove
|
2023-07-19 11:30:26 +08:00 |
|
RuigeLee
|
e3e1f6b6cb
|
a new top for fpga; port mac-master to mem
|
2023-07-17 21:41:34 +08:00 |
|