RuigeLee
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4bc5e2927e
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修改key策略
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2025-09-05 17:15:04 +08:00 |
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RuigeLee
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d5523eaa46
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Merge branch 'feature/clk3_shift_allow' into mp_eb_dev
# Conflicts:
# src/main/scala/backBoard/ebus/CDRIn.scala
# tb/shinTest/ShinTopSpiTb.v
# tb/shinTest/gen_pkt.py
# tb/shinTest/testcase/base.py
# tb/shinTest/testcase/environment.py
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2025-09-05 16:01:52 +08:00 |
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RuigeLee
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7ec88aa3a7
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Merge branch 'feature/8b10b' into mp_eb_dev
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2025-09-05 15:43:02 +08:00 |
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RuigeLee
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7b3b4c010d
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8B10B正负相写反
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2025-09-05 15:39:17 +08:00 |
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RuigeLee
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e9bc1d1e18
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cdrin的preamble连续监控10个cycle
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2025-09-05 15:09:52 +08:00 |
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RuigeLee
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adb1d9c1c8
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4b5b 8b10b接线完成
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2025-09-05 12:55:32 +08:00 |
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RuigeLee
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26344d60cd
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写完编解码模块
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2025-09-05 11:11:01 +08:00 |
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RuigeLee
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b1825607ab
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修复中断丢脉冲问题，但每次脉冲宽度比设置多一拍
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2025-09-05 09:58:43 +08:00 |
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RuigeLee
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f609945a6a
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8b10b编码完成
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2025-09-05 09:35:29 +08:00 |
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RuigeLee
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8a29acf4b8
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require是多余约束
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2025-09-04 16:40:07 +08:00 |
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RuigeLee
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4dd1841921
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cPtr需要同步复位
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2025-09-04 16:33:24 +08:00 |
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RuigeLee
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0b7bd505ba
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b5b6编码表
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2025-09-04 16:25:54 +08:00 |
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Ruige Lee
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6c56499f82
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主站发送的应该是加了offset的timestamp（reco）；softreset应该同步后输入异步口
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2025-09-03 19:08:48 +08:00 |
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RuigeLee
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cfed03b609
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增加主站offset寄存器用于多个主站校准时间
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2025-09-03 19:08:48 +08:00 |
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RuigeLee
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77da3d0507
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同步校准+spi lvds写入确认
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2025-09-03 19:08:48 +08:00 |
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RuigeLee
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1739cdb2a7
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删除localpoint和localperoid和中断2
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2025-09-03 19:08:48 +08:00 |
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RuigeLee
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6cf1e21774
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SM除错使用commit指针策略，需要测试覆盖1）一个包中同时写入操作0~4个sm的1~4个元素后出错，是否对后续SM操作发生影响，2）尝试在SM空时读，尝试在SM满时写，是否会对后续提交操作产生影响 3）寄存器0x538记录的时间不会区分是否是错误包4）在前述多次复杂操作后寄存器0x301的计数是否正常 5）从spi侧写入是否正常 6）主站写入的包错误将不会判断
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2025-09-03 18:04:10 +08:00 |
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RuigeLee
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32b73b8c93
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lvds读取锁，暂时只锁了ebmmu，sync相关寄存器需要等分支合并
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2025-09-03 16:26:58 +08:00 |
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RuigeLee
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cbd52792a5
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所有寄存器均复位
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2025-09-02 16:22:27 +08:00 |
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Ruige Lee
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a21d6eaf54
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确认波形
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2025-09-02 11:10:05 +08:00 |
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Ruige Lee
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60eec33b2d
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上下行交换特性
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2025-08-29 15:37:29 +08:00 |
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Ruige Lee
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51d29f1dd7
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Merge branch 'mp_eb_dev' into feature/dwupEx
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2025-08-29 11:12:53 +08:00 |
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Ruige Lee
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bbfc0322e9
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增加CDR仿真例程
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2025-08-28 20:03:42 +08:00 |
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Ruige Lee
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955fda6d05
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spi优化
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2025-08-28 18:00:20 +08:00 |
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Ruige Lee
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55ea876488
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同上
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2025-08-28 16:10:57 +08:00 |
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Ruige Lee
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659ab14fab
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修改同步点调整逻辑
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2025-08-28 15:53:17 +08:00 |
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Ruige Lee
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4b88e4937d
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改时序
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2025-08-28 15:51:17 +08:00 |
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Ruige Lee
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9bb59c350a
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Revert "Revert "改命令""
This reverts commit a0320e1993.
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2025-08-28 13:08:50 +08:00 |
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Ruige Lee
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a0320e1993
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Revert "改命令"
This reverts commit ea7ef3c9f9.
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2025-08-28 13:05:37 +08:00 |
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Ruige Lee
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ea7ef3c9f9
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改命令
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2025-08-28 13:05:17 +08:00 |
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Ruige Lee
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d4c793bf0b
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修正同步宽度不能spi修改的问题
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2025-08-28 11:07:57 +08:00 |
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Ruige Lee
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985407a8a4
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新spi设计
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2025-08-28 11:03:33 +08:00 |
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Ruige Lee
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f5336f1dc5
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硬件错误中断捕捉边缘
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2025-08-28 10:28:59 +08:00 |
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Ruige Lee
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706b9f17e5
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FPGA测试通过
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2025-08-27 17:06:31 +08:00 |
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Ruige Lee
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e44373ab83
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校准时间
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2025-08-27 16:31:17 +08:00 |
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Ruige Lee
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58ad17ce79
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修复
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2025-08-27 16:27:00 +08:00 |
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Ruige Lee
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a09ccef57f
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缩短主从同步时间差
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2025-08-27 16:05:20 +08:00 |
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Ruige Lee
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9773752cc8
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上下行交换特性
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2025-08-27 15:55:09 +08:00 |
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Ruige Lee
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fa3ba57f32
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spi写pll寄存器信号拉到顶层
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2025-08-27 15:20:43 +08:00 |
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Ruige Lee
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bdabf08108
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Merge branch 'mp_eb_dev' into feature/clk3_shift_allow
# Conflicts:
# src/main/scala/backBoard/ebus/CDRIn.scala
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2025-08-27 14:59:39 +08:00 |
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Ruige Lee
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dd71c557b7
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Merge branch 'feature/liftCdr' into mp_eb_dev
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2025-08-27 14:45:29 +08:00 |
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Ruige Lee
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4e2e3f6ca4
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修复sync的64位加法器输入位宽转换问题
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2025-08-27 09:42:01 +08:00 |
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Ruige Lee
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4b90a2c9bd
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CDR拉到顶层
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2025-08-26 17:52:23 +08:00 |
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Ruige Lee
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c6bd7902e7
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Merge branch 'mp_eb_dev' into feature/liftCdr
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2025-08-26 17:07:58 +08:00 |
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Ruige Lee
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b821571218
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同步逻辑扩展delta位宽，使用分时共享64位加法器
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2025-08-26 17:02:57 +08:00 |
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Ruige Lee
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ae99f5801d
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spi读锁定0x118
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2025-08-26 15:17:37 +08:00 |
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Ruige Lee
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6b118fa498
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spi读0x100将会暂存后续寄存器防止进位
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2025-08-26 11:35:47 +08:00 |
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Ruige Lee
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72fe230200
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尝试把CDR提到顶层
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2025-08-26 10:30:12 +08:00 |
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Ruige Lee
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6f1101f6dc
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改异步复位，增加flush接口，删除其他工程代码以编译通过
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2025-08-25 19:16:27 +08:00 |
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Ruige Lee
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7dd8458f96
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允许正负3个cycle偏移
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2025-08-25 17:32:21 +08:00 |
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