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cb0423e5ed
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增加用例的注释
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2025-09-17 22:00:44 +08:00 |
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0569733c44
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Merge branch 'mp_eb_dev' into new_spi
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2025-09-17 21:58:01 +08:00 |
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db799c5622
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增加代码，测试0xa的命令，方向正确，需要综合到FPGA平台上进一步测试。
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2025-09-17 21:55:53 +08:00 |
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RuigeLee
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759218b570
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修复微调方向
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2025-09-17 17:29:19 +08:00 |
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aa28113c07
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增加0xa协议子报文的测试,因为与时间相关,测试范围还较窄,目前仅仅是冒烟测试,貌似是过关的.
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2025-09-17 14:40:15 +08:00 |
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RuigeLee
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1e2fa0931d
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编译通过
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2025-09-17 11:07:34 +08:00 |
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RuigeLee
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21ffc1b58d
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spi跨时钟域
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2025-09-16 18:01:14 +08:00 |
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RuigeLee
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1dee4519bb
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增加同步子报文A；验证关注点1）变化增量的正负方向 2）deltafinal修正前后跨越正负 3）前仿真的综合行为
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2025-09-16 11:27:02 +08:00 |
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RuigeLee
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e83ba629b7
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优化cdrsim模式
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2025-09-15 17:47:31 +08:00 |
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bffe4fcab1
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makefile被覆盖,提交新的makefile
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2025-09-15 16:58:34 +08:00 |
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RuigeLee
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2ecb547bc8
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增加初版CDRIn方案
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2025-09-15 15:31:39 +08:00 |
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c9ece457e9
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增加sim cdr clk的生成python文件,支持在Makefile中动态生成相位和时钟偏差
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2025-09-15 09:09:35 +08:00 |
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RuigeLee
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958987ff6d
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参数化cdrInSample，支持4相位
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2025-09-11 18:57:58 +08:00 |
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RuigeLee
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99b9d9a72f
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修复CDRIn的异步复位
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2025-09-11 18:56:13 +08:00 |
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RuigeLee
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f42c9044d8
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添加分频io
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2025-09-11 15:50:38 +08:00 |
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RuigeLee
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d6ca17c75d
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更新忽略文件
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2025-09-11 15:17:12 +08:00 |
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RuigeLee
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ea7d91e9d3
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检回编译文件
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2025-09-11 15:15:47 +08:00 |
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RuigeLee
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45a77fca12
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移除rocket-chip子仓库
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2025-09-11 14:34:07 +08:00 |
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RuigeLee
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2c2898ae05
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简化sbt工程结构，删除多余makefile选项
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2025-09-11 14:30:58 +08:00 |
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RuigeLee
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26367fd63c
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删除其它项目设计文件
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2025-09-11 14:30:08 +08:00 |
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Ruige
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61d4f6fcf8
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Merge branch 'mp_eb_dev' of github.com:whutddk/RISCV-MAC-SWICH into mp_eb_dev
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2025-09-11 14:12:08 +08:00 |
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RuigeLee
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a24abbc098
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回滚修改
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2025-09-11 14:11:40 +08:00 |
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de0f5223c4
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增加新的测试用例以及相关的对比数据
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2025-09-11 11:59:17 +08:00 |
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RuigeLee
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d46e06d5b0
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代码整理
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2025-09-11 11:50:58 +08:00 |
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RuigeLee
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2969cf70a1
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取消3个寄存器只能配置一次的特性
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2025-09-11 11:28:05 +08:00 |
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Ruige
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f0e5895505
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Merge branch 'mp_eb_dev' of github.com:whutddk/RISCV-MAC-SWICH into mp_eb_dev
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2025-09-11 11:02:24 +08:00 |
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RuigeLee
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68f3c2ac89
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仅当sm为空时方可修改sm的触发长度，注意cnt=cPtr-rPtr，之前可能wPtr已经移动（可能撤销）
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2025-09-11 11:01:50 +08:00 |
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497c248507
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增加新的寄存器测试用例
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2025-09-11 10:36:30 +08:00 |
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139035e79e
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增加新的测试用例；错误恢复，增加对主站的对应的SM复位操作
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2025-09-10 23:42:04 +08:00 |
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RuigeLee
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f700b11e84
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latch使用主站offset校准后时间
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2025-09-10 09:12:52 +08:00 |
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47897f321b
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修正测试用例
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2025-09-10 00:53:55 +08:00 |
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RuigeLee
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e258cd4a6c
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优化spi，更严谨
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2025-09-09 18:06:14 +08:00 |
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Ruige
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ba04725e72
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Revert "尝试跨时钟域QSPI，失败"
This reverts commit 5ccf101648.
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2025-09-09 17:50:22 +08:00 |
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RuigeLee
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5ccf101648
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尝试跨时钟域QSPI，失败
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2025-09-09 17:48:52 +08:00 |
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Ruige
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42139b5bcc
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Merge branch 'mp_eb_dev' of github.com:whutddk/RISCV-MAC-SWICH into mp_eb_dev
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2025-09-09 16:11:57 +08:00 |
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RuigeLee
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22cc6ef0b8
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微调spi访存时间点，提高理论极限频率
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2025-09-09 16:10:19 +08:00 |
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58b65da129
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增加8b10b的测试用例，并与4b5b共享测试用例
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2025-09-09 01:21:02 +08:00 |
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b51b56688a
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调整异频异相时钟的测试参数
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2025-09-08 23:41:59 +08:00 |
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cc51f206de
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修正clk仿真的代码，可以通过测试
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2025-09-08 23:17:29 +08:00 |
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Ruige
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2b1f01274b
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Merge branch 'mp_eb_dev' of github.com:whutddk/RISCV-MAC-SWICH into mp_eb_dev
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2025-09-08 21:50:15 +08:00 |
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RuigeLee
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a6a546a0f9
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完成对4b5b，8b10b的覆盖测试
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2025-09-08 21:49:56 +08:00 |
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73b773e286
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对顶层文件中的错误修改,使得仿真可以正常运行
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2025-09-08 18:51:41 +08:00 |
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fa1327aa5f
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修改测试用例数据,回归通过
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2025-09-08 18:25:05 +08:00 |
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31b362b291
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增加8b10b打开关闭的开关
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2025-09-08 18:25:05 +08:00 |
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RuigeLee
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561f394b16
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sReg.isLVDSWriteAble 锁定lvds写入syncPoint和synccfg
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2025-09-08 17:48:08 +08:00 |
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Ruige
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43b70e674c
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Merge branch 'mp_eb_dev' of github.com:whutddk/RISCV-MAC-SWICH into mp_eb_dev
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2025-09-08 17:10:09 +08:00 |
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RuigeLee
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1d5a257b58
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Merge branch 'mp_eb_dev' into feature/syncSpi
# Conflicts:
# src/main/scala/backBoard/shin/SpiInterface.scala
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2025-09-08 17:07:10 +08:00 |
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RuigeLee
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c3c3a25e77
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修复spicmd没有在每次传输前后复位地问题，或许将导致三态门状态错误
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2025-09-08 17:02:43 +08:00 |
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9c43daf51e
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为多相位模拟增加命令行,增加8b10b切换的测试
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2025-09-08 16:47:30 +08:00 |
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a63e14e6f6
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增加代码,1.仿真了最多202个从站,功能正常;2.测试了读写\广播等操作
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2025-09-08 13:12:18 +08:00 |
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